in the program (EWB) its works
but at real life its sometimes doesnt.
Ive been told that there is another way.

Waiting for help :]

 

one way i can think of is to drive the clock of the ff by using a divide by ten counter but i think the logic behind it is the same ,
if we cud know why exactly does it not work in real life may be we can think of a way to compensate for that, like its a problem unique to asynchronous counter may be changing to a synchronous counter may help (dont know for sure my knowledge in electronics esp in practical cases is limited)

 

I didnt realy understood, can you paint it please?
(circuit Diagram)

 

ok,
i think the previous idea won't work well because a divide by ten counter is again a decade counter (what i meant was using a divide by ten counter to
divide the frequency of pulse generator by ten and then give it to the ff)
and as you say using a decade counter may not always work,
the synchronous counter design is quite tedious and i dont know whether it
wud help or not.

have u learned about ring counters or shift registers,
here is a way to deal with the clock frequency problem but it wud require
ten additional d flip flop.
what a ring counter does is shift the a pre loaded (logic one at input)
from first ff to the last ff per clock pulse thus we can have a division of the pulse generator frequency by ten which can be then given to the tens first ff.
if u want to take a look at how a ring counter looks/works follow this link.

http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#bcd

its easy to understand how it works.the link might also explain what i meant by use of divide by ten (n) counters.

(this is just an idea - since i m a noob when it comes to electronics try waiting for better answer)

 

Ive been told that the answer isnt synchornizem conters.

 

what abt ring counters then?

i myself wasnt sure of synchronous counter. what i thought was the problem with divide by ten counter not functioning properly as u are saying might have
been from the additive time delay that is introduced in case of asynchronous clocks which is absent in case of synchronous one.

edit: what exactly is the problem in using the present arrangement ,is it that the clock pulse width wud be quite low?
just wondering, try giving the clock pulse with the last ff of second's units ( i m not sure but for a negative going edge it might work)

 

I didnt really understood your idea.
Can you maybe paint it?

I have wires of the FF's Q , and when its reach ,1010 (for example) I want
to Clear all the FF and to tell the next FFs level to grow.

I connect a wire to an AND GATE that checks if the Q's in: 1010 status.
and this wire connected to all the CLRs and to the next level FF's first CLK input.

I need a replacement for this.
something else.