I am studying these diagrams:


I don't understand why on the figure (c) above, the current through Q2 flows upwards. This is NMOS transistor and the current should flow from its drain towards the source. If as in this case, we have a negative voltage applied to its gate, the I would expect the current flow to be limited (limited because this is small signal analysis, normally for DC I would expect a cut off), and therefore a larger current through Q1. So in other words Id of Q2 should flow downwards with a magnitude lower than Id of Q1. Why it is not the case?

 

The id's are small signals. In Q1 and Q2, the DC (or large signal) D->S currents are I/2. If the D->S current deviates from I/2 by a small amount, the difference is considered a small signal. In (c), I/2-id is the real D->S current of Q2; hence id is marked as going upwards. Besides, id can be either negative or positive. When VG1>VG2, id is positive; and on Q2, its D->S current is lower than I/2, as the upward id "cancels" part of I/2. When VG1<VG2, id is negative; and Q2 sees a larger D->S current, as the upward but negative id "enhances" I/2.

 

Why it is not the case?

it totally is the case but you are hanging on that too much so that you are not following the method of calculations and underlying rationale. the method uses mix of large and small signals which are calculated separately. large signals use capital letters, small signals use lower case letters.

the voltage at source of Q1 and Q2 is not zero. it floats up and down based on actual inputs. but when circuit is at some equilibrium, we do not know that voltage exactly. so calculation involves some assumptions. one of them is that Q1 and Q2 are perfectly matched which of course is impossible. then it is assumed that currents through both of them are equal... roughly that is the true but in reality that is also never the case.
so if 50% through each Q is 50uA, that is a perfect balance. and it is called "large signal". then when some imbalance is created, currents could be 51 and 49uA. but since both Q1 and Q2 are biased at the mid point of 50uA, the small signal is then +1 and -1uA.

 

I am studying these diagrams:
View attachment 351751

I don't understand why on the figure (c) above, the current through Q2 flows upwards. This is NMOS transistor and the current should flow from its drain towards the source. If as in this case, we have a negative voltage applied to its gate, the I would expect the current flow to be limited (limited because this is small signal analysis, normally for DC I would expect a cut off), and therefore a larger current through Q1. So in other words Id of Q2 should flow downwards with a magnitude lower than Id of Q1. Why it is not the case?

You need to take a step back and revisit what small-signal analysis is. You are trying to impose a large-signal interpretation to the small-signal portion.

The whole idea behind small-signal analysis is to operate a non-linear circuit in such a way that the time-varying signals of interest are sufficiently small that we approximate a circuit as behaving like a linear element superimposed on a constant element and then use superposition to analyze the two components separately.

As you say, the TOTAL currents in both are flowing downward, with, in general, one being larger than the other. But both have to sum to the output of the current source (let's call that Iss.

i_D1 + i_D2 = Iss

When you analyze the circuit with no differential input voltage, you find that both transistors have half this current (by symmetry, if nothing else).

I_D1 = I_D2 = I_D = Iss / 2

When there is a positive differential voltage, the current in Q1 will increase

i_D1 = I_D1 + i_d1 = I_D + i_d1

The current in Q2 will also change and, in general, will be

i_D2 = I_D2 + i_d2 = I_D + i_d2

However, we still have that requirement that the total sum of the currents must equal Iss

i_D1 + i_D2 = Iss = (I_D + i_d1) + (I_D + i_d2) = 2*I_D + (i+d1 + i_d2) = Iss + (i+d1 + i_d2)

But this requires that

i_d2 = - i_d1

To simply things, we simply give i_d1 the name i_d and define the this portion of the current in Q2 as i_d flowing the other direction (to take care of the minus sign).



i_D2 = 8 mA

 

Thanks for all the answers. Yes, the minus sign in the right hand side, drain current convinces me but still have some doubts, especially when looking at this:


Later, author claims that the decreased current of Q2 actually contributes to the increased output current, adding up to Q4s current. First, it looks odd, because we have two currents in the same wire flowing in the opposite direction - not very realistic. Second, even assuming it is some simplification, how can a decreased Q2 current increase output current? Q4 is a current mirror and will always source current "i". Q2 is now not sinking "i" anymore so entire current of Q4 will go to the output, but this is "i" not "2i". What do I miss here?

 

You don't have opposite currents flowing in the same wire. You have two different wires connected to a third wire. Think of it like you kitchen faucet. You have hot and cold water lines combining at the faucet. Now imagine that the values are tied together so that adjusting the hot results in the same flow from the cold. So if you adjust the hot to output 1 gal/min, the cold also outputs 1 gal/min and the total output will be 2 gal/min.

Aside from that, you need to keep in mind that the currents being discussed are small changes to the overall currents.

 

You don't have opposite currents flowing in the same wire.

No? Ain't drains of Q4 and Q2 connected by the same, one wire? Yet I see two different currents flowing in the opposite direction in that wire.

Think of it like you kitchen faucet...

I hear you but not sure this is a good analogy here. Cold and hot water come from different sources, here we have a situation where we have one source/power supply, yet it generates opposite currents.

Aside from that, you need to keep in mind that the currents being discussed are small changes to the overall currents.

Yes but even this is something I question, and here is why: this is a differential amplifier right? If so, we indeed have some small signal on the input, however the output signal (and this is exactly the mut point here, where both i currents combine to 2i) is not longer a small signal right? It got amplified.

 

No? Ain't drains of Q4 and Q2 connected by the same, one wire? Yet I see two different currents flowing in the opposite direction in that wire.

Again, it is not one wire. You have an output. Another wire that is connected between Q2 and Q4. So the current in the drain of Q2 does not have to be the same as the current in the drain of Q4. Any mismatch flows either into or out of the output wire.

I hear you but not sure this is a good analogy here. Cold and hot water come from different sources, here we have a situation where we have one source/power supply, yet it generates opposite currents.

In my house, the hot and cold water both come from the same source -- a single pipe coming into the house from the water company. All of the water eventually flows out a single pipe going to the sewer.

And you are still getting hung up on insisting that those SMALL currents are the TOTAL current. They are NOT! They are small CHANGES in the overall total current.

So let's look at the total currents for a moment.

Let's first consider the case where the inputs are the same (i.e., no differential input voltage is applied, just a common-mode voltage).

Let's say that this results in a drain current in Q1 and Q2 of Io=10 mA (just to keep numbers simple).

The current in Q1 is mirrored by Q3/Q4 to produce a drain current in Q4 of 10 mA.

Since these are the same, there is no output current because all of the current coming out of Q4 is consumed by Q2.

Now, let's take the gate voltage on Q1 up by a small amount, call it ΔV, and take the gate voltage on Q2 down by the same amount.


This results in the drain current in Q1 going up by a small amount, ΔI (let's assume it goes up by 1 mA, making it 11 mA), and the drain current on Q2 going down by the same amount (making it 9 mA).

The mirror outputs the same current as the drain of Q1, namely 9 mA.

So now, coming into the output junction, we have (Io+ΔI) = 11 mA coming down from Q4 and we have (Io-ΔI) = 9 mA.

KCL requires that the current going out the output must be the difference, namely 2 mA (or 2*ΔI).

Mathematically, I can write the current (Io+ΔI) as the sum two currents, one that is equal to Io and the other that is equal to ΔI. I can do the same for the other currents that are the sum or differences of currents. This allows me to draw things as follows:


The total current in a wire is the algebraic sum of all of the component currents in that wire.

The red currents are the bias currents (the large-signal, or DC, currents), while the blue currents are the signal currents (the small-signal, or AC, currents).

The notion of representing a total current as the sum of component currents should not be new to you. You should have done this when you studied superposition and mesh current analysis and you should have done this LONG before you every heard of transistors.

At the end of the day, "small-signal analysis" is nothing more than an application of superposition by treating the total response of the circuit as the superposition of two sets of inputs -- the power supplies and bias circuits as one set, and the input signal as the other set. But superposition is only valid for linear circuits, so we require that the signals be small enough that we can treat the circuit as being approximately linear about the operating point imposed by the power supplies and bias circuits.

Yes but even this is something I question, and here is why: this is a differential amplifier right? If so, we indeed have some small signal on the input, however the output signal (and this is exactly the mut point here, where both i currents combine to 2i) is not longer a small signal right? It got amplified.

The notion of "small signal" merely means that our system is working with voltages and currents such that the deviations (the "small signal") from the quiescent (the "bias" or "large signal) conditions are sufficiently small such that the non-linear behavior of the components involves can be acceptably modeled as linear deviations. The actual magnitudes of the signals that satisfy this requirement vary significantly from one part of the circuit to another. In some parts, the voltage changes must be comfortably smaller than the thermal voltage (this is in BJT-based circuits), otherwise the nonlinear characteristics assert themselves strongly. But, in other parts of the circuit, the deviations can be many voltage because changes of that magnitude, at that point in the circuit, do not involve significant nonlinear deviations.

 

Thank you for this response, it's very clear. I see the direction and magnitude of Q2 mathematically. The biggest problem I had was to accept that the small signal current of Q2, during a negative voltage swing on its base/gate sort of "changes direction" to flow upwards to the output. It was just more logical to me that since Q2 doesn't sink this signal current due to limited conductivity, then we have just current i from Q4 at the output.