Differences between various AND chips?

Discussion in 'Digital Circuit Design' started by StrongPenguin, Jun 22, 2018.

  1. StrongPenguin

    Thread Starter Member

    Jun 9, 2018
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    I've bought a whole bunch of chips for my computer project, but I see the numbers and letters on the chips come on various "versions".

    For example, I have an OR gate marked MM74HC32N and MC74HC32N (Same chip!) So I was wondering if this differs from 74LS32.

    Of course the data sheet lists the various differences there may be, but I am thinking, Is there like a rule of thumb, that "they are all the same, besides for x or y"?
     
  2. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    There is a difference in manufacterer between the MM (Fairchild) and the MC (Motorola , now ON).
    The HC is highspeed cosmos and LS is low power scottky.

    Bertus
     
  3. crutschow

    Expert

    Mar 14, 2008
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    The CMOS HC devices have significantly different logic levels and fanout than the LS devices, so you have to be careful if you want to mix them in a circuit.
    Generally you want to avoid mixing them if possible.
     
  4. dl324

    AAC Fanatic!

    Mar 30, 2015
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    Unless you know what you're doing, you shouldn't mix CMOS and TTL gates.

    TTL outputs aren't guaranteed to drive CMOS inputs without a pull-up resistor. CMOS outputs have a fan out of 1 or 2 when driving TTL, maybe even 0 for 74S.
     
  5. StrongPenguin

    Thread Starter Member

    Jun 9, 2018
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    Ok. That doesn't sound like something I should worry about with my little project.

    What about ending letters? Some end with P, other N, or M. I can only see things regarding packaging..

    EDIT: This may explain why I had problems getting the circuit to act the way it should. I had one INV LS04, AND LS08 going into an OR HC32 and from there to a D-Triggered Latch 74LS75. Could also be wrong wiring, ofc.
     
    Last edited: Jun 22, 2018
  6. ebp

    Well-Known Member

    Feb 8, 2018
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    The suffix letters designate the package and there is no broad consistency from one manufacturer to another. "P" is typically a plastic dual in-line (DIP or DIL), N is usually the same thing. M usually designates a surface mount package, but be very careful - there may be several variants in terms of pin spacing and overall size, designated by additional characters following the M. Some manufacturers use D as a suffix for some surface mount parts.

    The prefixes generally go back a long way. SN was TI's prefix for TTL. MM was National's for CMOS. CD was RCA's CMOS. MC was used by Motorola for a lot of devices, including most of their analog ICs.

    In the CMOS families, there are "T" parts available in some series. These are designed to have "TTL-compatible" input voltage levels when operated at 5 volts. The base part numbers are things like 74HCTxx, 74ACTxx. The ACT series actually has higher output drive and is faster than standard and LS TTL. The non-T HC and AC CMOS devices will drive TTL [EDIT: when operating at 5 volts] but don't have TTL-compatible inputs.

    You will definitely save yourself grief if you don't mix families until you have learned the intricacies. Sometimes if you mix "incompatible" devices things will work fine sometimes then quit working - changes in supply voltage and/or temperature can change behavior when things are right at the ragged edge. This can lead to huge frustration.
     
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  7. dl324

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    Here is why interfacing 74LS to 74HC isn't guaranteed to work.

    74LS08 output specs:
    upload_2018-6-22_15-0-48.png

    74HC32 input specs:
    upload_2018-6-22_15-2-13.png

    74LS08 VOH can be as low as 2.7V (3.4V typical). 74HC VIH must be at least 3.15V. So a typical 74LS output can drive 74HC directly, but one at the minimum of 2.7V can't. To guarantee that all 74LS can drive 74HC, you must use a pull-up resistor on 74LS outputs.

    If you use 74HCT, you can interface with 74LS directly. 74HCT is 74HC with TTL input specs.
     
    Last edited: Jun 22, 2018
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  8. KeepItSimpleStupid

    Distinguished Member

    Mar 4, 2014
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    Here https://en.wikipedia.org/wiki/Logic_family is a list of logic families. It's very brief.
    Such things like speed, sourcing current, sinking current, fan in, fan out, input current all matter.

    TTL compatible may only be valid when the supply is 5V.

    Prefix was mostly the manufacturer, the suffix the package and the middle stuff the family. With all of the mergers, that isn't necessarily true. Parts beginning in SE might sub to those beginning in NE.
    A CMOS 555 timer is WAY different than a 555 timer.

    Here's http://www.ti.com/lit/ds/symlink/ne555.pdf a whole bunch of 555 timers with different prefixes.
     
  9. StrongPenguin

    Thread Starter Member

    Jun 9, 2018
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    Thanks for all the feed back.

    This is the measly little circuit I can't seem to get to work. I can't find any wrong wiring, but I will spend a little more time looking.

    Could anyone help me with the pull ups/down? I have tried before the OR gate, but that just locks the Q.

    1-bit-reg.jpg

    EDIT: Ok, It works now. It was error 40. Some words on the pull ups would be much appreciated, though :)

    EDIT2: On second edit, no, It doesn't work quite as it should. Sometimes when I unplug D1, it registers 1 bit, when it just should halt.
     
    Last edited: Jun 23, 2018
  10. ebp

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    Feb 8, 2018
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    I'll leave others to help you with why it doesn't work, but ...

    DeMorgan's Theorem is very useful:
    in words
    not (A AND B) = (not-A) OR (not-B)
    not (A OR B) = (not-A) AND (not-B)

    By applying DeMorgan's to your circuit, you would require only NAND gates (other than the flip flop,of course):
    NAND instead of AND outputs LOW instead of HIGH when both inputs are HIGH (TRUE)
    A NAND gate is, by DeMorgan's, a "negative-OR" gate - if either input is LOW then the output is HIGH

    If you called the inputs to your AND gates A, B, C and D and the output from the OR X
    X = (A*B) + (C*D) using the gates as drawn
    X = /(/(A*B) * /(C*D)) = (A*B) + (C*D) using all NAND gates and applying DeMorgan's Theorem
    * = AND
    / = inversion (NOT)
    + = OR

    You can also use a NAND gate with both inputs tied together or one for the input signal and the other tied HIGH instead of an inverter. Doing this gets you down to all the gates you need in a single IC, instead of 3 different ones.

    EDIT: If you added an inversion "bubble" at the output of each of your two AND gates and bubbles at each input of the OR gate, it would be drawn in the preferred way when using NAND gates and applying DeMorgan's Theorem. Drawing that way makes if very easy to see that the inversion bubbles "cancel."
     
    Last edited: Jun 23, 2018
  11. dl324

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    What was the resistor value? Were they pull up or down? Until you are more experienced, I'd recommend that you use 74LS32 instead of 74HC32. Doing that will make things simpler.
    What are you unplugging D1 from? Is the input to that AND gate ever allowed to float?

    You can't allow the inputs of any gates being used to float. It's best to not leave any inputs floating. Best case, they'll cause increased power dissipation.
     
  12. dl324

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    If you have 74LS00, DeMorganizing the circuit, as suggested by @ebp, would eliminate potential problems with interfacing 74LS to 74HC. An added benefit is that you eliminate 2 packages if you aren't using unused gates from those IC's elsewhere.
     
  13. MrChips

    Moderator

    Oct 2, 2009
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    Some logic families are compatible and some are not.
    Until you learn and understand the differences, it would be best not to mix families. A general basic rule at the fundamental level would be not to mix CMOS logic with non-CMOS logic. For example, don't mix 74HC with 74LS.
    74HC is CMOS (that is what C stands for).
    74LS is not CMOS.
     
  14. bertus

    Administrator

    Apr 5, 2008
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    Hello,

    The attached PDF will tell you more about the properties of cmos and TTL chips.

    Bertus
     
  15. StrongPenguin

    Thread Starter Member

    Jun 9, 2018
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    @ebp It was just a schematic I followed on a video series on making an 8bit Computer. The purpose was just to emulate a 4-bit register chip. I just followed the wires. But thanks for simplifying the circuit for me, that's just what I'm trying to study now.

    @dl324 Sorry, it is when I unplug Load from Low, it just "activates" without needing it be High.

    The resistors are 1K. I've tried both pulling up and down on the out puts of the AND gates, but it seems to act the same.

    It stores value on the "bus" when, when Load is high, and doesn't do anything if it's low. The only thing I find funny is the if none of the wires are plugged, it starts out with a 1 bit register (Led is lit up..) if I unplug and plug. Even if I Load a 0-bit.

    I think next time I will just make sure I get only LS gates. Are there other things I should be aware of, regarding LS gates, do they all play together just fine without up/down resistors?
     
  16. Pedant Engineer

    Member

    May 27, 2018
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    There is nothing connected to the clock input of the D-type flip flop. The random operation could be related to that and possibly a bypass capacitor problem. LS devices are very very sensitive to power supply fluctuations and they can generate some pretty nasty current spikes. You must get the bypass cap placement right on the power pins.
     
  17. StrongPenguin

    Thread Starter Member

    Jun 9, 2018
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    Thanks for the PFD, @bertus, and thanks for help all.

    I will consider this case closed, and move on with the project. I learned a whole lot from it, as you usually do when things don't work :)
     
  18. StrongPenguin

    Thread Starter Member

    Jun 9, 2018
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    There was a clock connected.
     
  19. dl324

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    In general, it's easier to discuss circuits if you post schematics. Schematics should include all components in the circuit so we can eliminate obvious things from the discussion.

    If you're using switches to change inputs, we need to see that you're debouncing the switches and that you're not allowing inputs to float for some switch positions. Same if you're plugging and unplugging wires. We need to see what the circuit looks like with the wire plugged in and with it unplugged. Inserting/removing wires can also cause "bounce" because the wire could make/break connection multiple times for each make/break attempt.

    I think others have mentioned in some of your previous posts that pull-down in't preferred in TTL because inputs are often the emitters of NPN transistors and there will be some current coming out of the pins. That will cause a voltage to appear across a pulldown resistor and the value of that resistor needs to be small enough that the drop won't raise the input above what's considered logic LOW. Using a resistor that's an unnecessarily low value makes it harder for whatever is driving it to pull it HIGH.

    LS TTL is getting expensive and is still relatively power hungry. I'd convert it to CMOS if I was to undertake a project like this.

    Make sure to use an appropriate power supply distribution method so voltage drops don't become an issue. LS TTL operates from 4.75-5.25V, CD4xxx operates from 3-15V.

    My first job was building HP computers that were the size of a refrigerator using TTL for everything except memory. The main 5V supply in that computer was rated for 100A.
     
  20. crutschow

    Expert

    Mar 14, 2008
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    Until you fully understand the differences between the two logic types and how to interface the two, you should use only one type in your circuits.
    Otherwise you will likely continue to have problems with the circuit operation.
     
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