Hello
I attach two schematics. Which one offers better performance? The difference is the placement of some resistors. But, what are the advantages and disadvantages?

 

I prefer the second circuit because the bias resistor R2 can be selected such that the output transistor is off when the leakage of IC1 is excessive.

 

The first is not a proper circuit.
It can zap the opto output transistor since there's no resistance to limit its collector current from the PNP's base-emitter junction to the power supply.

The second is okay, since it has a limiting resistor.

 

The opto output can also be in the emitter if the reverse logic is required and a NPN used, but I prefer to use a mosfet if possible, starting with the 2n7000.
Max.

 

For the second circuit (Second.PNG) image in post #1, should I calculate resistor values again if I want 24V instead of 12V?

 

For the second circuit (Second.PNG) image in post #1, should I calculate resistor values again if I want 24V instead of 12V?

In general, yes.