DFF using Mux - did I do it right?

Thread Starter

nettek

Joined Jun 4, 2018
16
I am studying for an interview for FPGA engineer (first time position) and am trying to solve some problems/questions in preparation.
One question I encountered was implementing a D Flip Flop using a Mux.
I did it this way, but haven't seen any solution that resembles my own, so I wanted to ask if it is okay, and if I haven't missed anything.

DFF-MUX.JPG

D is basically the selector for the first Mux, and if clk is '1', then the result goes to Q. if clk is '0', Q stays at it's current state.

I wanted to also ask something else - how do you approach digital design questions? I am having a hard time with this. I barely know how to begin, and am trying to answer by trial and error. Is there some way to approach them logically?

Thank you!
 

crutschow

Joined Mar 14, 2008
24,403
What type of multiplexer is this?
Your circuit requires a digital one with an active output such as an 74HC157, not a switch feedthrough type, which many CMOS types are.
But that may be what a FPGA mux is.
With such a digital mux your circuit should work (see LTspice simulation below).

But what's the purpose of the mux on the left?
Can't you just feed the D input directly to the second mux?

upload_2018-10-6_19-25-59.png
 
Last edited:

andrewmm

Joined Feb 25, 2011
167
I am studying for an interview for FPGA engineer (first time position) and am trying to solve some problems/questions in preparation.
One question I encountered was implementing a D Flip Flop using a Mux.
I did it this way, but haven't seen any solution that resembles my own, so I wanted to ask if it is okay, and if I haven't missed anything.

View attachment 161048

D is basically the selector for the first Mux, and if clk is '1', then the result goes to Q. if clk is '0', Q stays at it's current state.

I wanted to also ask something else - how do you approach digital design questions? I am having a hard time with this. I barely know how to begin, and am trying to answer by trial and error. Is there some way to approach them logically?

Thank you!

Great your thinking components,
the number of new engineers that try to program FPGAs in C like , and wonder why a pointer is not working...

Fpgas would traditionaly be coded in an RTL e.g VHDL or verilog

and there are two major FPGA companies, Xilinx and Altera ( now intel )

Have a look at their free tools and tutorials ,for examples
 

AnalogKid

Joined Aug 1, 2013
8,314
There is no need for the first mux stage. The D input is either a 0 or 1, and is selecting a 0 or 1.

Also, your circuit does not emulate a true D flipflop because the output follows the input when the clock is held in the 1 state. This is called a transparent latch. A common part number is the 74LS373.

http://www.ti.com/lit/ds/symlink/sn74ls373.pdf

Also, there is a possible error condition when the clock signal is changing from 1 to 0. Depending on the mux internal circuit, the output might not stay in a valid logic state (0 or 1) as the mux transitions from one input to the other.

ak
 

Thread Starter

nettek

Joined Jun 4, 2018
16
Thank you for the answers.

First, do remember it's a question given at job interviews - they don't care about part numbers.
Also, this means it's theoretical, so there is no consideration in possible errors like clk signal staying in '1', or anything else like that. Everything is ideal.

I know this isn't the best answer - the best solution is one with one mux, where the signal D is fed directly to the mux. But, this is the solution I came up with, and just wanted to know if it's okay or not.

Also you're ignoring my second and more important question :)
how do you approach digital design questions?
 

Thread Starter

nettek

Joined Jun 4, 2018
16
But where do you start?

Say you need to design a divide by 3 frequency divider. How do you even begin planning the circuit?
 

crutschow

Joined Mar 14, 2008
24,403
Say you need to design a divide by 3 frequency divider. How do you even begin planning the circuit?
You need to know some basics, such as a toggle FF circuit will divide by 2.
Then you determine the number of FF's and the logic required to get a divide by 3.
Generating a logic-state/truth table can help.
Google "sequential logic design".
 
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