# Design of Mode-20 Counting Circuit

#### Hoozy94

Joined Apr 26, 2018
17
Hi all!

I've got a design problem I'm hoping someone can help with.

Part of a project is to design a mod-20 counting circuit using D flip flops, and then again with JK flip flops. The only issue is I'm not as knowledgeable as some when it comes to digital logic circuits.
I've got the truth tables/karnaugh maps for the D type, but I'm unable to derive the circuit from this.

Could anyone please show me the way?

#### dl324

Joined Mar 30, 2015
17,011
Welcome to AAC!

Is this homework?

In any case, post your work.

#### Hoozy94

Joined Apr 26, 2018
17

No, this is something extra that I'm working on to get better at this subject, in preparation for my dissertation! I hope what I have so far is correct.

#### dl324

Joined Mar 30, 2015
17,011
You said you were to design with D FF and then with JK. It appears that you're using T.

I 'm assuming that the data to the right of the excitations data is meant to be some form of Kmap. It would be helpful if you used the standard format.

I find it easier to transfer data from the truth table to Kmaps if you order the rows in gray format.

I'm going to treat this like homework; you'll learn more that way.

#### Hoozy94

Joined Apr 26, 2018
17
So I'm not even using the right type of flip flop? That's not a good start!
Yes, is indeed. What is the standard format for a 5-variable k-map?
I'm not sure what you mean by order the rows in gray format?

#### dl324

Joined Mar 30, 2015
17,011
What is the standard format for a 5-variable k-map?
There are a couple ways to do it. I use this format that I was taught more than 40 years ago:

(This map isn't for a mod 20 counter.)

What you're likely being taught is to use 2 4x4 maps that you overlay to make groupings.
I'm not sure what you mean by order the rows in gray format?
In gray code format, only one variable changes between rows. If you're populating Kmaps by hand, this format makes it easier to transfer data because Kmaps are also ordered in gray code format.

#### Hoozy94

Joined Apr 26, 2018
17
I've been following the reading material for my course called 'Fundamentals of Logic Design', and I must have followed the module for the T type instead of the D. I haven't actually been taught any of this, this is all for my own learning. Probably explains my initial difficulty haha!
I'll have another read through and try again. Thank you!

#### dl324

Joined Mar 30, 2015
17,011
I haven't actually been taught any of this, this is all for my own learning.
Is there a reason why you're trying to perform exercises for things you haven't yet covered in class? AAC members may have different, but equivalent, ways of doing things. That won't really be helpful to you if your instructor expects you to do it the way s/he teaches.

AFAIK, no one teaches the method I use, but I've used it to solve for 6 variables. Beyond that, I'd start using the overlay method.

#### Hoozy94

Joined Apr 26, 2018
17
Is there a reason why you're trying to perform exercises for things you haven't yet covered in class? AAC members may have different, but equivalent, ways of doing things. That won't really be helpful to you if your instructor expects you to do it the way s/he teaches.

AFAIK, no one teaches the method I use, but I've used it to solve for 6 variables. Beyond that, I'd start using the overlay method.
My dissertation will focus on this topic, which is why I'm trying to make a head start on learning the required skills. The method will not matter as long as the result is correct and relevant. Plus, the sooner I get this done, the sooner I can concentrate on other bits of work

#### dl324

Joined Mar 30, 2015
17,011
Your choice regarding how to proceed. You can finish the implementation with T FF, or start over with D or JK.

BTW, your truth table doesn't make sense. You said you were designing a mod 20 counter (0,1,2,3,4,...,17,18,19,0,...). This table doesn't follow that sequence:

I assume what you've labeled as CLK was supposed to be count.

You're also missing the don't care rows which would allow some logic simplification.

#### Hoozy94

Joined Apr 26, 2018
17
Yes, you're correct. the CLK was supposed to be the count. My bad, still learning!
I don't really understand the don't care rows. I assume I'm supposed to keep the counts in that aren't in my desired counting sequence and just label them as don't care? Then that would make it easier to group them..?

I am required to use D and JK so I'm restarting with the D type now.

#### dl324

Joined Mar 30, 2015
17,011
I'm restarting with the D type now
Is the count sequence supposed to be 0,1,2,3,4,5,6,7,11,12,13,15,16,19,22,23,24,26,27,31,0,...?

#### Hoozy94

Joined Apr 26, 2018
17
This is all I have been given to practice with. From my understanding I need to first do a truth table, then a kmap, and then simplify, then derive the circuit?

Yes that's my counting sequence! Forgive the Microsoft paint skills

#### Hoozy94

Joined Apr 26, 2018
17
I hope this is starting to look better? Yellow highlight refers to the don't care values that aren't on my counting sequence.

#### Hoozy94

Joined Apr 26, 2018
17

Something along these lines?

#### dl324

Joined Mar 30, 2015
17,011
I hope this is starting to look better?
You haven't treated the don't care counts correctly.

You should learn how to change column width, center data, and use cut and paste.

I take it that you've been taught to use A as the most significant bit. That's the opposite of what the industry uses.

#### Hoozy94

Joined Apr 26, 2018
17
Instead of having the 'don't care' values next state as the next one I actually want in the count sequence, should I have them as simply the next state as it usually would be without the specific count sequence? ie 01000 -> 01001 rather than what I have which is 01000 ->01011.

That's formatting, I'm more bothered about the theory and understanding what's happening.

I'm not sure what you mean by the most significant bit. I'm also unsure as to what that diagram is apart from the title of it.

#### dl324

Joined Mar 30, 2015
17,011
Instead of having the 'don't care' values next state as the next one I actually want in the count sequence, should I have them as simply the next state as it usually would be without the specific count sequence? ie 01000 -> 01001 rather than what I have which is 01000 ->01011.
It depends on the counter requirements. You definitely don't want 8 to go to 9. Whether you have 8 go to 11 or don't care depends of whether you have requirements for counting out of invalid states. Typically we'd make 8 a don't care for potential logic simplification.
That's formatting, I'm more bothered about the theory and understanding what's happening.
I find it difficult to read when poor formatting and extraneous information/color coding are used.
I'm not sure what you mean by the most significant bit. I'm also unsure as to what that diagram is apart from the title of it.
In the counter schematic I posted, 'A' is the least significant bit and 'D' is the most significant. It becomes important when you try to use a BCD to seven segment decoder (74LS47) that labels it's inputs like this:

#### Hoozy94

Joined Apr 26, 2018
17
I definitely do not want it to count to anything not on the counting sequence. So in that case it's correct the way it is? Or should I remove the 'don't cares'?
Ah, sorry the formatting is just rough as this is all just draft idea's and theory
I think that stuff is a little bit out of my know-how at the moment. You're obviously much more knowledgeable on the subject so I'd like to keep it simple so I can learn!

Last edited:

#### dl324

Joined Mar 30, 2015
17,011
So in that case it's correct the way it is?
The state diagram you posted didn't show any requirement for counting out of incorrect states, so I'd take that to mean that they were don't cares.