# Design of a BCD counter.

#### gato pro

Joined Sep 18, 2020
18
Hi, I need a little help, I have to design a module 39 natural bcd counter, which when energizing the circuit starts at 24.
Using two 74ls160, which is a synchronous bcd counter, with asynchronous clear.

What occurred to me is that, since I need to start counting at 24 and have modulo 39, the final counter would be 24 + 39 = 63, so it would count from 24 to 62 and thus I can have modulo 39 as they ask me.
To do this, using the inputs of load DCBA (8421), I want to preload 0010 in the tens counter and 0100 in the ones counter, but to obtain the combinational logic I would have to make a table D1 C1 B1 A1 D0 C0 B0 A0 | / LOAD and when you have 24 (0010 0100) the / LOAD input would be 0, and then minimizing by Karnaugh, you would get a gated array for the / LOAD input. Is there a simpler way to preload 24, without having to solve K'maps for so many variables? Thanks!!

#### ericgibbs

Joined Jan 29, 2010
13,654
hi gato,
Have you considered a Pload of 24 decimal into the counters when the logic is powered On.
E

#### gato pro

Joined Sep 18, 2020
18
Hi ericgibbs, thanks for answering, yes, I was thinking about that, use a power on reset so that when the circuit is energized it activates the parallel load and precharges the 24, but when it reaches 62, I don't know how to make it return to the parallel load to start again at 24 and so the cycle is continuous.

#### MrChips

Joined Oct 2, 2009
24,233
What you need is an OR function.
You want the counter to parallel load on power on OR 62 reached.

#### ericgibbs

Joined Jan 29, 2010
13,654
hi gato.
How many states does a 39 Modulo counter have.?
Considering state 0 is 24.?
E

#### gato pro

Joined Sep 18, 2020
18
Hello again, I was able to make my counter start at 24, and with combinational logic that as soon as it reaches 62 it restarts, now my new problem is how to design, perhaps with a schmitt trigger, that the first pulse is at zero, to that the input / load of the counter takes 24, and then for 39 clock pulses it is high, so that the counter continues the sequence until 62.
I don't know if I explained well, I hope so.

#### dl324

Joined Mar 30, 2015
13,142
I was able to make my counter start at 24, and with combinational logic that as soon as it reaches 62 it restarts, now my new problem is how to design, perhaps with a schmitt trigger, that the first pulse is at zero, to that the input / load of the counter takes 24, and then for 39 clock pulses it is high, so that the counter continues the sequence until 62.

I don't know if I explained well, I hope so.
It would be clearer if you posted a schematic.

#### gato pro

Joined Sep 18, 2020
18
The counter must be module 39, and start at 24, that is, it would count up to 62 inclusive, therefore, with the two AND gates and the NAND, I detect 63 so that the counter as soon as it reaches 62 is reset. But my problem is that I put a pulse train to the / LOAD inputs of the counter (LHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH) to check if the circuit worked, which it is, but it is like a cheating way to make it work.
I need to make that pulse train with some component, so that in the first pulse it is in L, so that the load input starts with 24, and then the pulse goes to H so the counter follows the sequence until 62, and then restarts . But I don't know how to "transform" that pulse train into something that I can actually implement.

I upload a diagram of the circuit, and the proteus file, the extension is .txt since it does not allow me to upload files with that ending, change the .txt extension to .pdsprj I hope I am not violating any forum rule, If so, I apologize in advance.

#### Attachments

• 14.8 KB Views: 3
• 203.3 KB Views: 2

#### ericgibbs

Joined Jan 29, 2010
13,654
hi gato,
One obvious mistake in your circuit, you would not normally Reset the Counters to zero at the end count, reload the 24
E

Also the initial Pload is missing

#### gato pro

Joined Sep 18, 2020
18
If I do the precharge with a power on reset, for example, using a capacitor with a resistance at 5V so that the capacitor is barely charging, the active low charge input takes it as a logical low state and once the capacitor is charge completely, the charge input would be disabled. With combinational logic, I need to send a low signal as soon as the counter reaches 63, my problem is how to join the power on reset that is in a high state with a combinational logic, with the signal that detects state 63?

#### dl324

Joined Mar 30, 2015
13,142
I upload a diagram of the circuit, and the proteus file
Does Proteus support printing to a black and white PDF file or turning off the grid?

Proteus isn't a free program, so it won't be helpful to most of us.

Can you post the complete text for the problem so we know what you're required to do with respect to setting the counter to 24 initially?

#### gato pro

Joined Sep 18, 2020
18
The problem says:

Design and implement a module 39 natural BCD synchronous counter that starts at 24 when the circuit is energized, using integrated TTL-LS counters with asynchronous reset input.

#### Attachments

• 203.3 KB Views: 7

#### dl324

Joined Mar 30, 2015
13,142
The problem says:

Design and implement a module 39 natural BCD synchronous counter that starts at 24 when the circuit is energized, using integrated TTL-LS counters with asynchronous reset input.
How are you going to load 24 at startup?