I have this assignment that I don't have the slightest idea how to do it, and the teacher didn't really excelled at explaining it to us. I need to design a 5Kx8 memory module using 1Kx8 memory modules with one chip enable at active-low level in a 32K memory map, but starting at 3K address. Logic gates can be used for the design (no coders, muxes...). As far as I get it, the whole memory map is not used because my starting address is 3K, not zero. It would be very helpful if someone is willing enough to draw the design. Thanks in advanced!

 

Welcome to AAC!

For homework, you need to show your best effort before members will try to guide you to a solution.

 

Write out the memory addresses for 0K to 32K in 1K steps.
Find the 5K addresses you require and make a truth table for these. See what patterns are common and what are not common.

 

I have this assignment that I don't have the slightest idea how to do it, and the teacher didn't really excelled at explaining it to us. I need to design a 5Kx8 memory module using 1Kx8 memory modules with one chip enable at active-low level in a 32K memory map, but starting at 3K address. Logic gates can be used for the design (no coders, muxes...). As far as I get it, the whole memory map is not used because my starting address is 3K, not zero. It would be very helpful if someone is willing enough to draw the design. Thanks in advanced!

Uhm... isn't drawing the design what YOU are supposed to do?

How many address lines do you need?

How many address lines does your module need?