so I am stuck on this problem and cannot wrap my head around how I would implement this. I need to design a 2 bit register that can be operated according to the following function table

S0 S1
0 0 no change
0 1 clear register to 0
1 0 complement output
1 1 load parallel data

I believe that it will require two 2-1 multiplexers and two d flip flops. this is as far as i have gotten but am confused as how to continue. Can anyone explain how I would design this thank you.

 

0 0 no change <-- don't care
0 1 clear register to 0 <-- this function will be a problem, because the register only can count up from 00 to 01, so the 10 and 11 will never show up.

1 0 complement output
1 1 load parallel data

 

so I am stuck on this problem and cannot wrap my head around how I would implement this. I need to design a 2 bit register that can be operated according to the following function table

S0 S1
0 0 no change
0 1 clear register to 0
1 0 complement output
1 1 load parallel data

I believe that it will require two 2-1 multiplexers and two d flip flops. this is as far as i have gotten but am confused as how to continue. Can anyone explain how I would design this thank you.

You need a dual 4:1 mux and set the inputs to each mux as follows:
0: Q output from the flip-flop for 'no change'
1: 0 input to clear both flip-flops
2: Q' output from each flip-flop to complement
3: Parallel data Input