so I am stuck on this problem and cannot wrap my head around how I would implement this. I need to design a 2 bit register that can be operated according to the following function table
S0 S1
0 0 no change
0 1 clear register to 0
1 0 complement output
1 1 load parallel data
I believe that it will require two 2-1 multiplexers and two d flip flops. this is as far as i have gotten but am confused as how to continue. Can anyone explain how I would design this thank you.
S0 S1
0 0 no change
0 1 clear register to 0
1 0 complement output
1 1 load parallel data
I believe that it will require two 2-1 multiplexers and two d flip flops. this is as far as i have gotten but am confused as how to continue. Can anyone explain how I would design this thank you.