Hi all,

I want to develop a delay generator which can delay input pulse by 20us to 50us. (Input pulse=80us)
I have tried LTC6993 and LTC6994 on LtSpice tool. But didnt get the desired output.
Please suggest me a suitable circuit.

Thanks in Advance.

 

The pulse is 80uSec and you want to delay it by a variable amount (controlled by what?).

What do you want to happen if a second pulse starts before the first delayed pulse is still in progress?

Do you want the delayed signal to delay start by 20-50uSec and still take the full 80uSec or should the end come early so the system is ready to accept a second pulse?

Is this logic level and milliamperes or what is driven by this delayed signal? What is the source of the original signal?

 

The pulse is 80uSec and you want to delay it by a variable amount (controlled by what?).

What do you want to happen if a second pulse starts before the first delayed pulse is still in progress?

Do you want the delayed signal to delay start by 20-50uSec and still take the full 80uSec or should the end come early so the system is ready to accept a second pulse?

Is this logic level and milliamperes or what is driven by this delayed signal? What is the source of the original signal?

Well there will not be second input pulse before the delayed output. The input source is a SRS Signal Generator. The delay can be variable.

 

hi pnp,
Please post your LTspice asc file.
E

 

Hi pnp,
This circuit is one option.
E

 

@ericgibbs,
How wonderful is that I thought about two methods and the one was as you did, another one is using a PNP circuit to replace the second 555, but I'm not sure if the C9 is too small, does the circuit will work properly or not.

 

Can the output pulse be an independently generated 80 us that is delayed and triggered by the leading edge of the input pulse? (Two Monostables)

or

Must both edges of the input pulse be delayed so that any small variations in its pulse width appear at the delayed output? (Delay Line)

ak

 

hi Scott,
The Low period of the Trigger pulses look OK, these are CMOS devices.
I have added a diode across the Trigger input resistor to clamp the positive spike.
E

 

hi pnp,
If you need to use a potentiometer to set the Delay period, this option uses a linear charge current for the timing capacitors.
E

 

What is the purpose of Q2 and Q4? They look like firmly saturated (Ic/Ib = 4.3), always on switches.

And, do we know that regenerating an 80 us output pulse, whose width is independent of the input pulse width, is acceptable to the TS?

ak

 

hi,
Not knowing which method the TS was going to use for controlling the 555's, it's possible to control Q2 & Q4 On/Off IF required.

Perhaps if and when he posts back, we can firm up the circuit.?
E

 

if If IF output pulse regeneration is acceptable to the TS, here is something I posted on another forum last month. For this thread, timing components R3, R4, C1, R5, R6, and C2 need to be adjusted for the much shorter timing periods.

Also, R1, R2, D1, and Q1 can be eliminated. D2 and D3 are optional depending on how much time the circuit has to recover between inputs.

The circuit can be adapted to a positive-going input edge by connecting pin 1 of R4 and R6 to Vcc.

ak

 

Here is a version that delays both edges of the input pulse rather than regenerating it at the output with a monostable, For a one time-constant delay, the adjustment range is 19.8 us to 52.8 us.

It looks nice, but will need modelling or prototyping to confirm. The issue is that the amount that timing capacitor C1 charges beyond the U1B upper or lower the trip point, before the next signal reversal, varies inversely with the amount of delay. This *might* make the output pulse width vary as a function of the delay period. The root cause is that the delay period is a significant and variable portion of the input pulse width. This probably is nothing, but I thought it best to bring it up.

Almost any Schmitt trigger gates will work, and they need not be inverting as long as they are the same. In a 5 V system, a 74HC14 or 74AC14 will work just as well.

ak

 

tried LTC6993 and LTC6994

http://beta-tools.analog.com/timerblox/LTC6994
Happy that day!

 

Hi pnp,
This circuit is one option.
E
View attachment 263498

Hi Eric,

Thanks, Could you please share the TLC555 library file. I have downloaded a Pspice model and imported to LTspice but its not working also has different pin nomenclature.

 

Hi Eric,

Thanks, Could you please share the TLC555 library file. I have downloaded a Pspice model and imported to LTspice but its not working also has different pin nomenclature.

I would like this as well.

 

Here is a version that delays both edges of the input pulse rather than regenerating it at the output with a monostable, For a one time-constant delay, the adjustment range is 19.8 us to 52.8 us.

It looks nice, but will need modelling or prototyping to confirm. The issue is that the amount that timing capacitor C1 charges beyond the U1B upper or lower the trip point, before the next signal reversal, varies inversely with the amount of delay. This *might* make the output pulse width vary as a function of the delay period. The root cause is that the delay period is a significant and variable portion of the input pulse width. This probably is nothing, but I thought it best to bring it up.

Almost any Schmitt trigger gates will work, and they need not be inverting as long as they are the same. In a 5 V system, a 74HC14 or 74AC14 will work just as well.

ak
View attachment 263524

This looks good. Do you have simulation file?

 

Hi @plugnplay
This is the complete list of all my files for the TLC555.
Some are duplicated.
If you have any problems, please ask.
E
The Help File is by 'Helmut'

@k1ng 1337

Added: 7555 files [also a CMOS device]

 

Below is the simulation of AK's circuit, modified using diodes and feedback to essentially reset the C3 timing capacitor (red trace) at the end of the delay (yellow trace) so there is no significant interaction between the input/output pulse-width and the delay timing.

 

Nice. I started with a different third-gate scheme, but took it out to keep things simple for a first-pass introduction to the concept.

With feedback around U6, there is no need for any Schmitt trigger gates; just about anything will work.

ak