Decoupling caps on VDD AND VSS???

Thread Starter

spinnaker

Joined Oct 29, 2009
7,835
I have always placed a decoupling cap on my VDD pin as close to the pin as possible. But I was looking over the datasheet for my pic and noticed this:

The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS
Exactly what does that mean? Do I really need a decoupling cap on VSS? How would that work exactly? Would I tie it to ground? That does not seem to make much sense to me since I would be basically shorting out the cap. Would I tie is it to VSS?

Or does is simply mean I need a 1 cap on the VDD pin just like I have been doing?
 

AnalogKid

Joined Aug 1, 2013
8,487
Vss (like its bipolar counterpart Vee) is connected to GND for logic chips,and you are correct - there is no such thing as decoupling it to the signal ground because it is the signal ground. But there are other devices where it is connected to a separate supply rail such as -5V or -12V. This is particularly true for CMOS opamps. In those cases, decouple the doors off of it.

ak
 

dl324

Joined Mar 30, 2015
10,975
I think they're telling you to decouple every power pin on a device with multiple VDD, VCC, and/or VEE pins.

If we knew which PIC, wouldn't have to guess.
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,835
PIC18F47J53

There is no schematic. I is a datasheet.

This is what it says

The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 F in parallel with 0.001 F).
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance
 

Papabravo

Joined Feb 24, 2006
13,926
The coupling capacitor goes between a pair of pins. One pin is Vdd and the other pin is Vss. On many PC boards it is convenient to have a pair of pads close to the chip which are then routed to the appropriate power planes.
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,835
The coupling capacitor goes between a pair of pins. One pin is Vdd and the other pin is Vss. On many PC boards it is convenient to have a pair of pads close to the chip which are then routed to the appropriate power planes.
So just put a cap between pin 20 VDD and pin 19 VSS? Which is basically what I am doing.

What do I do with pin 8 vss1? Just ground it? Pin 5 is VDDCore and I know that needs a 10uf cap.
 

Papabravo

Joined Feb 24, 2006
13,926
Decoupling caps are normally done in parallel. You need a high value one to provide current demand on the ins and you need smaller one to bypass high frequency noise to GND. I would use 1 uf in parallel with .1 uF in parallel with .01 uF.
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,835
Decoupling caps are normally done in parallel. You need a high value one to provide current demand on the ins and you need smaller one to bypass high frequency noise to GND. I would use 1 uf in parallel with .1 uF in parallel with .01 uF.
Datasheet calls just for a .1uf
 

Lestraveled

Joined May 19, 2014
1,946
There are few strategies about placement of decoupling caps.
Idealistically, this is how I do it: Generally there is a power entry point on the board. This is where I will put 10uF tantalum in parallel with a .1uF ceramic. I will use a "star" distribution for Vcc and a ground plane for the return. At the point of each star, I will put a .1uF to the ground plane. Any part that is high speed gets their own .1uF cap. Any part that draws a lot of current gets a lot more capacitance.

.1uF caps are cheap, use a lot. There is no down side.
 

Lestraveled

Joined May 19, 2014
1,946
A "star" is where you establish a low impedance at the power entry point with the tantalum and .1uf capacitors. This is the center of your "star". You will then run "arms" out to the different areas of your board to supply power. At the end of each "arm" there should be a .1uf cap (or more). The reason for this "topology" is the noise generated in each "arm" is not spread to other "arms". This is a far better topology than daisy chaining all the power pins together.
 
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This is done to improve the dynamic current distribution inside the chip. You simply MUST connect all VDD and VSS pairs to your power supply and decouple each pair with 0.1 uF ceramic capacitor placing it as close as possible to the VDD/VSS pin pair.
 
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