DDS waveform with Synchronised phase Start

Thread Starter

TomHBP

Joined Feb 5, 2021
5
Hi all.
I am building a system with multiple units that must produce a synchronised audio swept output. Synchronization is done via central clock signal, but audio generation is produced locally.
My first thought was to use AD983x DDS modules. This works, but the waveform (starting at 10's of Hz, and sweeping to 10's or 100's of kHz) always 'begins' at a random phase point by which I mean the lowest frequency begins at a random phase degree.
When many units are together, this might cause destructive wave boundaries.
I have tried sleeping and resetting the AD9834, as well as adjusting the phase register, but noting will get the sweep to reliable start from 0°.
Does anyone know of a chip that could achieve this? PWM to a sine wave might work, but even at 12-bit PWM output, I would get terrible resolution at 100's of KHZ.

Any ideas welcome,

Many thanks,
Tom.
 
The data sheet says that the reset pin sets the analog output to midscale but doesn't clear frequency or phase settings. Isn't that exactly what you need?

Or, how about driving a discrete ADC, like an AD5660, from a microcontroller? That might be easier than taming the DDS.
 

michael8

Joined Jan 11, 2015
332
AD9834 datasheet:
https://www.analog.com/media/en/technical-documentation/data-sheets/AD9834.pdf
https://www.analog.com/en/products/ad9834.html

From looking at the datasheet my guess is that with the chip held in reset you can set a
configuration (frequency, phase and control register settings). The accumulator which
isn't addressable sounds like it is held at zero during reset.

Then you need to release reset on all the chips at the same time. If they are all starting
with an accumulator of 0 and the same frequency and phase they should be in sync.

The easest way to release reset would be with the external reset pin. There might
be a way to do this with parallel control writes in sync...

I'd look at the "sign bit out" MSB mode to see if they were in sync.

I wonder how slow MCLK can be run, possibly a microprocess could provide
a slow/manual MCLK and watch "sign bit out" to determine the accumulator value
and stop when the MSB just turned on. With them all in sync the run full speed
MCLK.

Oh, I sse the problem, every time you change the frequency they would get out of sync
unless you figure out a way to write each exactly in parallel...

Perhaps it would be easier to distribute the signal from a single point?
 

tmig1

Joined Apr 9, 2018
1
Hi Tom,

I have done a fair amount of work with DDS for chirps, FSK enocding, and staright CW output using ADxxxx chips, as well as building my own using inexpensive micros. I will try and help if I can.
I am a bit vague on exactly what you are trying to do, so if you would be willing I could use a bit more detail.
- What chip controls/programs the AD9834?
- Can you show a trace of what exactly you mean by a "synchronised audio swept output(s)"?
- Are you somehow using the AD9834 to do a sweep of frequencies and mixing them with local audio?
- You write "Synchronization is done via central clock signal". When you connect multiple units do they share the AD9834 MCLK as the central signal?
- What is your maximum frequency oupt of the AD9834?
- Are you using the square wave or sign wave output?
- What is the worst case random phase degree offset you are seeing?

Best Regards,
Tom
 
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