Howdy,
How do I simulate this LTspice circuit? I would like to plot current vs time at the drains of U2 and U3 as VBAT sweeps from 4.2-3.0V.
Circuit Description: Low battery monitoring that cuts off its own power supply a short time after turning off U3
The theory:
1) Fresh battery is connected and switch is closed (if necessary) to turn ON U2
2) As VBAT drops below 3.1V, U3 is turned OFF and load is disconnected
3) U2's gate remains charged for some time via C1 to ensure the SR latch has completed its operation
4) U2 turns OFF and quiescent current of the entire monitoring circuit is minimized, ideally 0A

I have included the models for the logic gates as I had to find ones with power pins. Any help is appreciated.
Regards,
Mark
How do I simulate this LTspice circuit? I would like to plot current vs time at the drains of U2 and U3 as VBAT sweeps from 4.2-3.0V.
Circuit Description: Low battery monitoring that cuts off its own power supply a short time after turning off U3
The theory:
1) Fresh battery is connected and switch is closed (if necessary) to turn ON U2
2) As VBAT drops below 3.1V, U3 is turned OFF and load is disconnected
3) U2's gate remains charged for some time via C1 to ensure the SR latch has completed its operation
4) U2 turns OFF and quiescent current of the entire monitoring circuit is minimized, ideally 0A

I have included the models for the logic gates as I had to find ones with power pins. Any help is appreciated.
Regards,
Mark
Attachments
-
2.6 KB Views: 5
-
4.9 KB Views: 3