Because your Darlington stage is saturated.
https://electronics.stackexchange.c...base-there-is-more-than-one-vce/355955#355955
You have a 9V supply voltage a silicon diode + 470Ω resistor and Darlington C-E in series.
So the maximum current can't be larger than 9V/470Ω = 19mA. If we ignore all the remaining components.
But we have a voltage drop across the diode and the Darlington stage. Thus,
I_max ≈ (Vsup - VD - Vce(sat))/R3 ≈ (9V - 0.7 - 0.7V)/470Ω ≈ 16mA

View attachment 321292

Thank you for the clarification.
I also read the link you sent me but it's still not clear to me why you assumed Vce(sat) = 0.7V ... usually we talk about 0.2V for saturation.
The reason is related to the discourse that "Vce(sat) = 0.2V is written in books but in reality is such a voltage reached"?

Thank you.

 

Thank you for the clarification.
I also read the link you sent me but it's still not clear to me why you assumed Vce(sat) = 0.7V ... usually we talk about 0.2V for saturation.
The reason is related to the discourse that "Vce(sat) = 0.2V is written in books but in reality is such a voltage reached"?

Thank you.

The question of what constitutes "saturation" in a BJT can be a matter of heated debate. Part of this is that the transition from the active region to the saturation region is not a sharp one, so it leaves the door open for competing definitions, complicated by the fact that transistors are used for different purposes and the meaning of saturation that is most useful in one application might be completely irrelevant in another.

A nice, simple (and arguable simplistic) definition is that the transistor is in saturation if the base-collector junction becomes forward biased by even the slighted amount, which happens when the collector voltage is equal to the base voltage, and hence Vce = Vbe. But there is nothing really magical about this operating point -- the transistor behaves almost identically if it is a little bit on either side of this point. But it is in the vicinity that the behavior is starting to change significantly, and so many analog designers find it to be a useful bound for design purposes, though if they are really concerned about linearity, they often put an even more stringent bound on how small Vce can be. Another common definition, in practice, is that the boundary between active and saturation region occurs when the beta of the transistor has dropped below some specified threshold. But that threshold is, at the end of the day, arbitrary. For historical reasons, most small-signal transistor manufacturers measure their saturation performance at the point where beta is equal to ten, and lots of people use this as what it means to be in saturation. It's not a very defensible position, but it is both widely used and reasonable enough for most practical purposes that it goes largely unchallenged. Digital designers, on the other hand, are using the devices as a switch and so they are interested in driving it into hard saturation, which is where you get Vce values down in the 200 mV range for even considerably less, such as sub-50 mV.

Just as some textbooks use Vbe of 0.6 V, others 0.7 V, and others 0.65 V, different textbooks use different Vcesat values, typically either 0.2 V, 0.25 V, or 0.3 V. None of these are right, but none of them are really wrong, either. If the acceptability of your circuit's behavior depends upon which of these you are using, then you shouldn't be using any of them. Either your circuit is poorly designed, or it needs to be designed with a much better model of device behavior than these rules-of-thumb permit.

 

I also read the link you sent me but it's still not clear to me why you assumed Vce(sat) = 0.7V ... usually we talk about 0.2V for saturation.
The reason is related to the discourse that "Vce(sat) = 0.2V is written in books but in reality is such a voltage reached"?

Good question. The reason is simple. The value given by the books applies to situations when we have a single BJT small signal BJT.
But in your example, we have a Darlington pair. To solve this mystery we need to apply KVL to be able see why for the Darlington pair the Vce(sat) voltage cannot be smaller than Vbe.

From KVL we have:

Vce4 = Vbe4 + Vce3



Therefore, the minimum voltage at the Q4 collector appears when Q3 is saturated.
In this configuration, Q4 will never be saturated.
Q4 cannot lower its collector voltage below Vbe because it would mean that it turns OFF itself.
Thus, Vce4(sat) = Vbe4 + Vce3(sat).
I hope that now you see why for the Darlington pair the Vce(sat) voltage cannot be smaller than Vbe.

 

Yes, Jony130 is absolutely correct for the Darlington -- I was answering the more general question that I thought you were asking. If you go back and look at your other thread where you had a Darlington, you'll see that I used the same minimum value of Vce for the Darlington as the extreme and, IIRC, that a better minimum Vce for Q4 would be about 800 mV to 1 V to account for both Vbe of Q4 and Vcesat of Q3.