DAC with inverting AOP as BUFFER

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
Hello AAC,

I previously posted on AAC but only on the RF DESIGN section.
I am here because of a DAC BUFFER.

I am trying to drive a laser diode with :
a. 16 bits DAC
b. Inverting AOP as BUFFER

With the high output impedance of the DAC, I have replaced R45 and R49 with 200K resistor.
With the AOP TSB611, I got output at -0.8379VDC with input at +1.77VDC (with -2.5 VDC on the VCC- AOP pin).
With the AOP TSB712, I got output at -0.98VDC with input at +1.6VDC (with -2.63 VDC on the VCC- AOP pin).

My conclusion was that my differents AOPs wasn't big enough.
But when I look to the TSB712 datasheet, I see a typical Isink or Isource of 50mA at VCC = 5V / Tamb = +25 °C.

Anyone could explain to me the procedure to choose the right AOP?

POWER SUPPLIES
1658929651254.png

DAC & BUFFER (edition 0.0)
1658929630644.png
 
Last edited:

Papabravo

Joined Feb 24, 2006
19,329
You have chosen an unusual structure for a buffer amplifier, and you have not provided a DC path to ground for the inputs. How about telling us what you are trying to accomplish instead of throwing components on a drawing in the hopes that you can find something that will work.

Questions:
  1. Is the output from the DAC a current or a voltage? I could check the datasheet but I'm asking you to save time.
  2. Do you want an inverting unity gain buffer?
  3. What is the purpose of L14 and C37, and what is the meaning of NM next to C37?
 

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
Hello Papabravo,

Thank you for your answer.
Ok for the unusual structure. For the DC path, could you give me more explanation?

The product on design is an RFoG transceiver with 3GHz of bandwidth from near to DC to 3 GHz.
I am trying to polarize a laser diode with a negative voltage from -0.8 to -1.2 VDC with a maximum of 30 mA current.
The polarisation needs to be temperature compensated with precision to keep good RF linearity across industrial temperature range. It is why I chosen an 16 bits DAC.
Each product will be factory calibrated, so I am not looking for ultra precise AOP with low offset.

I'll answer to your questions:
a. The DAC output is "Voltage- Unbuffered " with an output resistance of 6.25 KR.
The recommended input resistance must be 205 MR. It seems very big to me.
b. Yes, an inverting unity gain buffer is ok for me.
My embedded power supply could deliver -2 VDC at 35 mA on a load, after the linear regulator.
It seems not enought, it is why I chosen rail to rail AOP.
b. L14 and C37 are typical RF bias tee. NM is equivalent to DNP.
 

Papabravo

Joined Feb 24, 2006
19,329
Read this article which explains the reason for the DC path to ground. It is to provide for the DC bias currents.
https://www.analog.com/en/analog-di...oblems-when-designing-amplifier-circuits.html

This one talks about the circuit for a non-inverting unity gain buffer.
https://www.analog.com/en/analog-di...oblems-when-designing-amplifier-circuits.html
Here the DC path is through the low output impedance of the amplifier. The non-inverting input can be AC coupled.

AFAIK there are no useful opamp circuits where a resistor connected to an input, or an output also connects to a supply rail
 

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
For the opamp circuits, sorry for the misunderstanding, below the right schema in edition 1.0, which I've used for all my test.
DAC & BUFFER (edition 1.0)
1659018776306.png
 

BobTPH

Joined Jun 5, 2013
5,803
The equation for your opamp cicuit is;

Vi = Vo + (3-Vo)/2
Vi = Vo + 3/2 - Vo/2
Vi = Vo/2 + 3/2
2Vi = Vo + 3
Vo = 2Vi - 3

Is this what you intended?
 

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
BobTPH,

No. I was looking for Vo = - Vi.
With my edition 1.0 schematic and 200K resistor, I got the right voltage at the AOP output (Vo=-Vi) but only with current less than 20 mA.
What I don't undestand is why the output voltage drop at -0.98VDC with approx 21 mA. I thought the AOP was too small, it is why I upgraded it to the TSB712 but I won only 100 mV.
 

BobTPH

Joined Jun 5, 2013
5,803
BobTPH,

No. I was looking for Vo = - Vi.
With my edition 1.0 schematic and 200K resistor, I got the right voltage at the AOP output (Vo=-Vi) but only with current less than 20 mA.
What I don't undestand is why the output voltage drop at -0.98VDC with approx 21 mA. I thought the AOP was too small, it is why I upgraded it to the TSB712 but I won only 100 mV.
Okay, you posted the corrected circuit while I was analyzing the original one. The corrected circuit is indeed s gain -1 buffer.
 

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
Okay, you posted the corrected circuit while I was analyzing the original one. The corrected circuit is indeed s gain -1 buffer.
Sorry for that.

About the voltage drop, I supposed that rail to rail AOP doesn't have waste voltage (or negligible).
With power supply of -2.5 VDC at 30 mA, I don't understand why my output drop at -0.98 VDC.
I supposed the maximum output current of the AOP has been reach... but the TSB712 has typical current of 50mA at Tamb.
 

BobTPH

Joined Jun 5, 2013
5,803
Hello Papabravo,

Thank you for your answer.
Ok for the unusual structure. For the DC path, could you give me more explanation?

The product on design is an RFoG transceiver with 3GHz of bandwidth from near to DC to 3 GHz.
I am trying to polarize a laser diode with a negative voltage from -0.8 to -1.2 VDC with a maximum of 30 mA current.
The polarisation needs to be temperature compensated with precision to keep good RF linearity across industrial temperature range. It is why I chosen an 16 bits DAC.
Each product will be factory calibrated, so I am not looking for ultra precise AOP with low offset.

I'll answer to your questions:
a. The DAC output is "Voltage- Unbuffered " with an output resistance of 6.25 KR.
The recommended input resistance must be 205 MR. It seems very big to me.
b. Yes, an inverting unity gain buffer is ok for me.
My embedded power supply could deliver -2 VDC at 35 mA on a load, after the linear regulator.
It seems not enought, it is why I chosen rail to rail AOP.
b. L14 and C37 are typical RF bias tee. NM is equivalent to DNP.
The original circuit does have a DC path to ground through the 3V power supply, and is a perfectly good circuit, with output as I computed in post #6. Here is a simulation. The red line is intentionally 0.1V above my calculated output so that it shows up. The green line is the simulation output.


1659020927944.png
 

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
The original circuit does have a DC path to ground through the 3V power supply, and is a perfectly good circuit, with output as I computed in post #6. Here is a simulation. The red line is intentionally 0.1V above my calculated output so that it shows up. The green line is the simulation output.


View attachment 272452
Thank you for the simulation.

So the edition 0.0 circuit is good (but potential current problem with the first AOP TSB611)
The edition 1.0 has a DC path problem.

Thing I can test is to update the AOP from TSB611 to AD8009 on the ed0.0 circuit , to exclude current limitation doubt.
Or add the DC path correction on my ed1.0 circuit (always with AD8009), it will be easier for the software team for the DAC SW.

I'll think about it, request for the right software update of the MCU, test we'll be done at the end of august.
 

Papabravo

Joined Feb 24, 2006
19,329
Yes, power supplies and opamp outputs are viable path to ground for bias currents. I've just never seen that configuration before. I realized this when considering a typical non-inverting unity gain buffer.
 

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
Yes, power supplies and opamp outputs are viable path to ground for bias currents. I've just never seen that configuration before. I realized this when considering a typical non-inverting unity gain buffer.
Ok Papabravo.

I just realized that the charge pump with the linear regulator are not well design to get constant negative voltage from 0 to 30 mA.
The non linear voltage drop can't work with the edition 0.0 circuit.

But it should work with the edition 1.0 circuit, what I need to take care of is the waste voltage of the AD8009 which is not a rail to rail op amp.
It seems basic but am I forced to simulate the AD8009 to find the waste voltage beetween Vcc- and vo for 30 mA?
 
Last edited:

Thread Starter

BRUNET Joss

Joined Nov 1, 2018
38
Ok Papabravo.

I just realized that the charge pump with the linear regulator are not well design to get constant negative voltage from 0 to 30 mA.
The non linear voltage drop can't work with the edition 0.0 circuit.

But it should work with the edition 1.0 circuit, what I need to take care of is the waste voltage of the AD8009 which is not a rail to rail op amp.
It seems basic but am I forced to simulate the AD8009 to find the waste voltage beetween Vcc- and vo for 30 mA?
Instead of the AD8009, I'll test the ADA4891-1. It seems to have all required features:
a. Rail to rail
b. Symetrical power supply
c. Sufficient output current

I'll see to add a second charge pump in parallal of the first one and maybe a negative linear regulator at -2.5VDC instead of -3VDC.
 

jlm1948

Joined May 19, 2014
15
Hello AAC,

I previously posted on AAC but only on the RF DESIGN section.
I am here because of a DAC BUFFER.

I am trying to drive a laser diode with :
a. 16 bits DAC
b. Inverting AOP as BUFFER

With the high output impedance of the DAC, I have replaced R45 and R49 with 200K resistor.
With the AOP TSB611, I got output at -0.8379VDC with input at +1.77VDC (with -2.5 VDC on the VCC- AOP pin).
With the AOP TSB712, I got output at -0.98VDC with input at +1.6VDC (with -2.63 VDC on the VCC- AOP pin).

My conclusion was that my differents AOPs wasn't big enough.
But when I look to the TSB712 datasheet, I see a typical Isink or Isource of 50mA at VCC = 5V / Tamb = +25 °C.

Anyone could explain to me the procedure to choose the right AOP?

POWER SUPPLIES
View attachment 272348

DAC & BUFFER (edition 0.0)
View attachment 272347
LED's and laser diodes have a very sharp I/V curve. Belos a certain threshold, current is very small. Once the threshold has been exceeded, current rises sharply, quickly reaching the curent limit of the opamp. For linear operation, they are supposed to be current-driven.
 

jeffl_2

Joined Sep 17, 2013
67
I don't have time to draw a proper schematic nor do I intend to design this for you. There's a schematic here that shows the proper TOPOLOGY (in a sense, now you don't really need the input voltage divider) for a second op amp stage that would work for you as a current source, but you just have to "move everything down" since where they show +15 volts is apparently where you would put ground, so you can pull current through the diode from the negative supply and up through the current source into ground:

https://www.instructables.com/Constant-Current-Source-with-Operational-Amplifier/

You have to make certain that you design the power supply with enough "compliance voltage" to accommodate all the voltage drops from the diode and the current source transistor. That would mean adding up the forward voltage of the laser diode, the sense resistor drop under maximum current and about another .7 volts for the base-to-emitter drop that the opamp has to provide, and making certain that the negative power supply is somewhat larger. You don't HAVE to use a PNP junction transistor, you could use a logic-level PMOS device but instead of .7 volts you would need to accommodate about 5 volts so you would need a larger negative supply voltage primarily for the op amp. As has already been said it's always really MUCH nicer to control the current of a forward-biased diode, especially a laser since the light output is pretty much proportional to the current, that might even mean you COULD get by with a lower-resolution DAC but I don't know exactly what your design criteria are. I hope I haven't confused you too much but as I said I just don't have time right now, maybe if you post something to propose I can review it later or something.
 
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