D vs JK Flip Flops in State Machine Design

Discussion in 'Digital Circuit Design' started by chazzjh, Apr 10, 2018.

  1. chazzjh

    Thread Starter New Member

    Sep 28, 2016
    6
    0
    I teach a high school Digital Electronics course. I'm not an EE, mostly self taught and am relatively new to the topic. We have covered combinational and sequential logic and are working on state machines. We did an exercise with JK flip flops and now we are working another using D flip flops. The analysis is easier with the D flip flops because it is not necessary to create the table of JK values for each flip/flop based on the state transition (i.e. the state transition can be used directly for a D F/F).

    While we were talking about the process the question came up about why you would ever use JK F/Fs if the analysis for Ds is easier. So I thought I would pose the question here.

    Any thoughts?
     
  2. crutschow

    Expert

    Mar 14, 2008
    22,482
    6,581
    There are some logical sequences that are not readily done with a D-FF by itself.
    For example, generating the toggle function by putting both J and K high. The function requires an additional gate with the D.
    And suppose you want one signal to toggle the FF high and a different signal to toggle it low. Again, that requires additional logic with a D.
     
  3. dl324

    AAC Fanatic!

    Mar 30, 2015
    8,516
    2,047
    Analysis of circuits using D FF may be easier, but I've found that logic is often simpler with the additional flexibility afforded by JK FF.

    I'll check my counter designs to see if I've done any with both D and JK FF to see if my impression is substantiated.
     
  4. WBahn

    Moderator

    Mar 31, 2012
    24,332
    7,600
    Different designs benefit from different things. In general (not always the case), a J-K based design uses fewer external logic parts just because of the added flexibility. Ideally, you would do every design both ways and then choose the one that is the better match. In practice, most people get adept at using one and almost never use the other -- a case of when the only tool you know how to use is a hammer, every problem looks suspiciously like a nail. In between are the folks that strive to develop of feel for what types of problems are probably better served by each and then make the decision (not guaranteed to be the best one) near the beginning of the design process.
     
  5. ebp

    Well-Known Member

    Feb 8, 2018
    2,332
    811
    With D flip flops, the level at D must be defined, either HIGH or LOW, for every clock event - there is never a "don't care" condition for D. With JK flip flops, the appropriate input need only be HIGH when its corresponding output will change state on the next clock (i.e.if Q is to go HIGH, J must be HIGH prior to clocking and K is "don't care"; if Q is to go LOW (not-Q goes high), K must be HIGH and J is "don't care"). Those "don't care" conditions generally allow simpler overall gating, even though there are twice as many inputs.
     
  6. chazzjh

    Thread Starter New Member

    Sep 28, 2016
    6
    0
    Thanks for all of the excellent answers.
     
  7. dl324

    AAC Fanatic!

    Mar 30, 2015
    8,516
    2,047
    @chazzjh
    Here's a decade up counter implemented with JK and D. It turned out I didn't have any examples of counters implemented with both JK and D, so I did one with D.

    Don't be concerned about the set and clear inputs on the flip flops not being connected. My simulator assigns a LOW to floating inputs and I take advantage of that to remove some clutter.

    JK:
    upload_2018-4-11_11-58-16.png
    D:
    upload_2018-4-11_11-58-43.png
     
  8. chazzjh

    Thread Starter New Member

    Sep 28, 2016
    6
    0
    Perfect, thank you. This will make it so clear to me students.
     
Loading...