D Flip-Flop Design (SPICE)

Thread Starter

keymie94

Joined Apr 12, 2016
8
Hi, anyone have some experience design flip flop in ltspice? Currently Im trying to design a flip-flop in ltspice unfortunately the output is not what I want
upload_2016-11-28_10-48-23.png
This is my design, for the transistors I'm using 45nm model : PMOS (l=45n, W=180n) NMOS (l=45n, 90n)
Parameters:
Vdd : 1.9v
clk : pulse wave with period 10ms

Output
upload_2016-11-28_10-52-54.png

the flip-flop triggered at both rising edge and falling edge, this is my first time using spice to design digital logics, any suggestions on what should i play around with in here. Thank you in advance
 

WBahn

Joined Mar 31, 2012
25,064
Your initial waveform may be due to start-up conditions.

Why are you using a PMOS switch in one feedback path and an NMOS in the other? Will either of those work well for both polarities of signal that needs to be stored?
 

Thread Starter

keymie94

Joined Apr 12, 2016
8
Your initial waveform may be due to start-up conditions.

Why are you using a PMOS switch in one feedback path and an NMOS in the other? Will either of those work well for both polarities of signal that needs to be stored?
from what i read, this is a master slave flip-flop so one of the latch is a low phase latch and other high phase latch...
upload_2016-11-28_12-58-23.png
the cycle look like this, i know that i should put transmission gate rather than just pass transistors, I've tried it but the result is still the same
 

WBahn

Joined Mar 31, 2012
25,064
And what, precisely, is wrong with the result? Is it that initial output that is part way between the supplies that goes to a firm output on the first rising clock edge?

Try putting in some initial conditions to give the charge-storage nodes a meaningful initial value.

You might also try buffering your signals with CMOS inverters/buffers so that you aren't contaminating the simulation with drive signals from ideal sources.
 

Thread Starter

keymie94

Joined Apr 12, 2016
8
And what, precisely, is wrong with the result? Is it that initial output that is part way between the supplies that goes to a firm output on the first rising clock edge?

Try putting in some initial conditions to give the charge-storage nodes a meaningful initial value.

You might also try buffering your signals with CMOS inverters/buffers so that you aren't contaminating the simulation with drive signals from ideal sources.
Thank you, it works when i drive the clk with buffer. Can i know what do you mean by contaminating it from ideal sources?
 

WBahn

Joined Mar 31, 2012
25,064
Ideal voltage sources can deliver an unbounded amount of current along with infinitely fast edges. That creates artifacts in some circuits because of charge injection into sensitive charge-storage nodes.
 
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