Current sink that has the same rise time over variable current

Thread Starter

analog_headache

Joined Mar 8, 2016
15
I am optimising a current sink circuit to be a bit more well behaved. In the typical circuit below you can see that it is a standard FET current sink that switches on and off by connecting the amp to the gate(The current is turned on and off quickly to drive an LED). What I am finding is that if I am using a a smaller range current say 0 to 1A, things are ok and my switching speeds vary between 400ns at low current to around 100ns at 1A. As the requested current goes up, the rise time goes down as there is more voltage over the sense resistor and more current through R4 to switch it faster. If I adjust the sense resistor to limit the current to 4A, the switching speeds increase to around 1.5us at low current due to the affect of R4. Up at 4A, the switching speeds are fine again. I can adjust the value of R4 down to speed things up and indeed I can get the switching speed at low current to around 300ns again. However, at higher currents the speed is now too fast and the fast switching and hookup wire parasitics are causing lots of spikes and resonance.

My question is, are there any simple modifications to the circuit below that can break the circuit's direct relationship between rise time and sink current. e.g. at 100mA current rise time 200ns, at 4A current rise time 200ns.

Any guidance from the experts on the forum would be gladly received.

upload_2018-4-20_14-28-19.png
 

Thread Starter

analog_headache

Joined Mar 8, 2016
15
Sorry took me a bit of time to get the ltspice circuit to respond in the same way. I have slightly modified the circuit to represent what I am doing. Just to re-iterate, I am optimising a fast switching current sink. It switches pulses of around 4us with rise and fall times of around 200ns with currents ranging from 50mA to 4A. I was wondering if it was possible to make the rising time more independent to current. At low current, the rise time (and initial delay) is much bigger than at higher currents. I have attached the LTspice circuit with a stepped value for the current control voltage input (the + input to the amp). If you look at the waveform of I(R1) against the switch on pulse V1, you will see the effect that I am on about. The transient sim is setup to only show one pulse.

On the PCB I am using an AD8063 which has a tri-state output. I switch this off and on to create the current pulses. On the LTspice sim I have represented this as S2 on the output of the amplifier.

Any help greatly recieved
 

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DECELL

Joined Apr 23, 2018
96
I see your mosfet has active turn on via the opamp contol loop and passive turn off via R2. When your switch is off, it opens the control loop which you have to resetablish every time you switch back on. You may want to consider a different control scheme.Like leaving the current source continually on and using a separate series mosfet to switch the ouput into the load. This switch could be actively driven to improve on off times. Driver ICs are cheap and very fast, dumping amps of gate drive in a few nanoseconds.
I'll try some simulatons of my own and post them at a later date.
The fast switching of current sources is a pig for sure!
 

ebp

Joined Feb 8, 2018
2,332
You may be able to improve the compromise by adding a small resistance in series with C1 or alternatively placing a small capacitor in parallel with R4.

You can't put a switch in series with a current source/sink without the error amplifier losing its mind and slamming to the rail.
 

crutschow

Joined Mar 14, 2008
25,269
Here's the circuit modified to control the input control signal instead of the output.
That keeps the loop closed and the rise and fall times the same for different current settings.
I also added R6 to eliminate some overshoot I observed on the signal rise.

upload_2018-4-25_12-13-7.png
 
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Thread Starter

analog_headache

Joined Mar 8, 2016
15
Firstly, Thank you Decell, Ebp and Crutschow for your replies. I do very much appreciate you taking the time to push me in the right direction.

Dcell: I have considered the mirror circuit you allude. In fact it does actually give me more control and prevents the overshoot on the rising edge because the opamp is 'ready' to go. I have tested this on the bench and it gives good results but it suffers from the same problem as the simple current sink that at lower currents, the rise time increases. I have attached my ltspice sim (current_sin_with_mirror.asc) of it for completeness. I am open to suggestions on a 'mosfet drive ic' and would like to hear your ideas. Throwing amps about with speed and control is certainly not trivial!

Ebp: Good suggestions. The resistor in series with the cap (as Crutschow said as well) seems to help with overshoot which is great. The speed up cap round R4 doesn't appear to have much affect.

Crutschow: Thanks for your suggestion. I had discounted that architecture but I now think I may have been to hasty. I have replicated the modified circuit and attached it below with a few modifications that I will talk about. As shown in the waveform in your post, the low current trace (green one) still is a bit sluggish. It takes 1.4us to start rising. It then takes 700ns to rise to its current value of 75mA. This compared to the purple trace which takes 265ns to rise to 4A and has no starting delay to speak of. Ideally I would like to see the yellow and green trace to start rising at the same time as the other traces. By modifying the circuit as below (and as attached in the file simple_current_sink_with_amp_input.asc), I have managed to improve the rising edge delay a bit. The resistor in series with the voltage source was delaying the edge. I have replaced it with a voltage controlled switch to allow me to use a stronger driver but keep it isolated from the pull down FET when it is on. The start delay is around 200ns on the low current waveform (75mA) and the rise time is 780ns The bad thing appears to be a violent spike on the falling edge which I can only mitigate with adding a 100pF cap on the + input of the amp and making R7 around 5K. This then adds the delay back in on the rising edge of 1.5us (whack a mole!).

upload_2018-4-26_11-45-54.png

If I could get rid of that spike on the falling edge without affecting the start delay, that would probably solve my issue. I will modify my test board to replicate this in reality.

Everyone's comments are very welcome on this issue

Thanks again
 

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AnalogKid

Joined Aug 1, 2013
8,540
In terms of the rate of change of the output current in milliamperes-per-microsecond (mA/us), what is the range of acceptable values? Is there on optimum value you would like to hold for all peak current conditions?

Part of what is going on in the circuit is that the rate of change of the output energy is changing, and you might be seeing opamp bandwidth effects in the output signal at high currents that are less significant at low currents. My approach would be to take Wally's approach and separate it into an adjustable voltage ramp generator followed by a fixed-gain voltage-to-current driver. For this to work, the voltage-to-current stage would have to be much faster than the fastest input voltage ramp so it can track it accurately. More complex, not the simple mod you asked for, but better control over the circuit parameters.

ak
 

ebp

Joined Feb 8, 2018
2,332
The trailing edge spike is likely charge injection via M1's gate-drain capacitance. Some mitigation might be possible by limiting the slew rate of the rise of the gate drive to M1. If charge injection is the problem and the control voltage must be switched, a better solution would be to use integrated analog switches designed for low injection. Try the model with a voltage controlled switch instead of M1 to determine if charge injection is the issue.

I think it likely that a significant portion of the turn-on lag is due to getting the output FETs gate-source voltage up to threshold, working against the "saturated" feedback cap on the amplifier. The simulation needs to look at some more voltages and currents, not just I & O. Try stepping the current without going fully to zero. Again assuming charge injection at the input, the output spike shows very fast response once the FET is in the linear region. The spike says the circuit can be very fast once you wake the whole thing up and pry it out of bed. . The gain at very high frequency may need to be rolled off by shunting R6 with a small capacitor.
 

Thread Starter

analog_headache

Joined Mar 8, 2016
15
AK- I would like better than 16A/us. Not sure I have that the right way about :-]. I would like my rise and fall times to be less than 250ns for a 4A pulse. For the initial circuit this was achievable but down at low currents the rate of change was about 0.1A/us (100mA in 1us). I would also like that initial start delay to be removed as has been shown in the latest circuit. Even 400ns would be acceptable.

Thanks for your response
 

ebp

Joined Feb 8, 2018
2,332
If it can be demonstrated that getting the amplifier and FET off the rail is a significant contributor to turn-on, a improvement may be possible by setting the minimum current to something very low, perhaps tens of micoramps, rather than fully off, if that can be tolerated. This would probably require a trim to cope with the amplifier's input offset voltage.
 

Sensacell

Joined Jun 19, 2012
2,587
If speed is the primary design driver, consider leaving the entire current sink alone, running at a constant current, then use a transistor switch to shunt the current around the LED.

The switch would see the Vf of the LED only, maybe 3 Volts.
 

Thread Starter

analog_headache

Joined Mar 8, 2016
15
Sensacell - Thanks for your reply. If only I didn't have the power constraint, this might work for me.

ebp: Great information there. You are correct that it is charge injection causing the tail on the falling edge. I did as you said and replaced the FET with the Voltage controlled switch and the tail went away. I think I need to test this on thePCB using an analog switch e.g. adg823.

upload_2018-4-26_15-56-55.png

Getting there :)
 

crutschow

Joined Mar 14, 2008
25,269
I agree that it's charge injection of the switch. When an ideal pulse source is connected directly to the opamp input, the output current exhibits a fast rise and fall time with no spikes.

But the adg823 has 15pC of charge injection which may still give some objectionable spikes.
Look for low charge injection switches with <1pC of injection such as this.
It has a 120Ω on-resistance but that should still be low enough to give a fast signal fall time.
There's generally a trade-off between the charge injected and the switches on-resistance.
 

Thread Starter

analog_headache

Joined Mar 8, 2016
15
I have now tested this circuit in reality and I am pleased to say that this approach seems to give me what I want (with one caveat). I still used the ADG823 as the switch to isolated the amplifier control voltage as I had these parts to hand. I also replaced the current controlling FET with an NPN (FZT849) as this reduced some spiking, probably from charge injection again. I now have a fast and symmetrical pulse that rises in around 150ns with virtually no delay from the low currents (50mA) to high currents (4A).

The only small caveat is that the LED won't go out completely when I have the amp control voltage set as 0. I measured the control voltage it and it is 0V (well as near as damn it). The base voltage of the npn is sitting at 0.54V which I suspect is letting a trickle of current through. I can mitigate it and get the LED to go out if I place a 240ohm resistor between the base and the emitter of current controlling npn Q1 (shown in my attached sim). This reduces the vbe to around 200mV when the control voltage is 0V and puts the LED out. It maybe has a little affect on the edges by putting a little step in them.

My question is, is this the way to do this to get the LED completely out or is there another way to do this?

Thanks again for your help

upload_2018-4-30_10-9-56.png
 

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danadak

Joined Mar 10, 2018
4,057
When you ground input to U1 NI input, what V do you see on base
of Q1.

The AD8061 states it is RRIO, but when you look at specs with a 2K
load its worst case .25V.......

Regards, Dana.
 

Thread Starter

analog_headache

Joined Mar 8, 2016
15
Dana,

Thanks for your reply.

The base of Q1 is measuring 0.555V on the PCB. This correlates with the sim which shows 0.543V. The non inverting input is 0V. On the PCB, the resistor between the inverting input of the amp and the sense resistor (R4 in the sim) has 0.4mV on the input to the amp and 0.2mV on the side connected to the 0.5ohm resistor to 0V.

Thanks
AnH
 

danadak

Joined Mar 10, 2018
4,057
When Vin = 0 the OpAmp has to force a Vbe in order to maintain its
Vinv input to also be 0. ie. it has to have the E-B junction of Q1 conducting.
That in turn causes some conduction in Q1.

Based on your measurements you have 400 uA running thru emitter,
more than enough to glow an led.

Go for a MOSFET vs bipolar ?

Regards, Dana.
 
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danadak

Joined Mar 10, 2018
4,057
Note the AD8061 can have as much as 6mV of offset, that would cause
worst case by itself 1.2 mA in the emitter. You might want to look at a better
OpAmp for this.

First do a first order measurement of the LED to see what ~ the threshold
of current where it starts glowing, throw in a big fudge factor, and back into
the needed OpAmp offset.

Or as suggested earlier use a R in parallel with LED to rob it of current.
Inefficient needless to say, but should work.

Regards, Dana.
 
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