Hello I am trying to implement the attched article.
I am have A biasing current dilema.
From the attached article there is a diagram shown bellow.
When we design the bias current, i know that DC bias current will not go threw a capacitor.
I=C*dV/dt
is the capacitor current is DC current or AC current?
Thanks.

 

I = C * dv/dt

is neither AC nor DC, it is merely the differential equation that applies to a linear capacitor and applies all the time, regardless of the type of signal.

 

Hello WBahn,yes , but i want to know whether the DC current that flows threw PMOS splits between NMOS and C_L or not?

 

Hello WBahn,yes , but i want to know whether the DC current that flows threw PMOS splits between NMOS and C_L or not?

Let's assume that it does. If you have a constant (i.e., DC) current flowing into C_L, what has to be happening to the voltage across it?

Is this consistent with how a circuit has to behave when in DC steady state?

What does that say about the DC steady state current in ANY capacitor in ANY circuit?

 

Hello WBahn,
Question 1:" If you have a constant (i.e., DC) current flowing into C_L, what has to be happening to the voltage across it?"
Answer 1: Load capacitor become open circuit

Question 2:
" Is this consistent with how a circuit has to behave when in DC steady state?"
Answer 2:
In DC Yes the in DC our capacitor will be open circuit , but in small signal AC, C_L capacitor will be part of the small signal gain behavior.

So slew rate in not for steady state but for transient.

In Transient our capacitor will "conduct current threw it"
Correct?
So in Transient the PMOS current goes splits between NMOS and the capacitor.correct?
Thanks.