# current biasing dilema in common source design of gm/id

#### yef smith

Joined Aug 2, 2020
498
Hello I am trying to implement the attched article.
I am have A biasing current dilema.
From the attached article there is a diagram shown bellow.
When we design the bias current, i know that DC bias current will not go threw a capacitor.
I=C*dV/dt
is the capacitor current is DC current or AC current?
Thanks.

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#### WBahn

Joined Mar 31, 2012
28,514
I = C * dv/dt

is neither AC nor DC, it is merely the differential equation that applies to a linear capacitor and applies all the time, regardless of the type of signal.

#### yef smith

Joined Aug 2, 2020
498
Hello WBahn,yes , but i want to know whether the DC current that flows threw PMOS splits between NMOS and C_L or not?

#### WBahn

Joined Mar 31, 2012
28,514
Hello WBahn,yes , but i want to know whether the DC current that flows threw PMOS splits between NMOS and C_L or not?
Let's assume that it does. If you have a constant (i.e., DC) current flowing into C_L, what has to be happening to the voltage across it?

Is this consistent with how a circuit has to behave when in DC steady state?

What does that say about the DC steady state current in ANY capacitor in ANY circuit?

#### yef smith

Joined Aug 2, 2020
498
Hello WBahn,
Question 1:" If you have a constant (i.e., DC) current flowing into C_L, what has to be happening to the voltage across it?"