CPU Addressing Modes

Thread Starter

CNC682

Joined Jan 23, 2015
27
Hi,

I have a question relating to Addressing modes about a motorola C68MX11 CPU Core:


1. Using the block diagram,outline how the processor would add two numbers held in ACC.A and ACC.B the result being stored in memory. Identify the addressing modes that would be employed in this addition?

2. Also what address range in hex could the pc access?

upload_2016-11-14_17-36-5.png


My solution: wouldn't know where to start on the first one, there are some addressing modes in the data sheet below but am not sure how they relate to addition.

The second question referring to the data sheet (link provided below) I think it is 0000H to FFFFH which is the 64 kbytes addressing range.

http://www.moxsyn.com/data_sheets/C68MX11 CPU Core Page.htm
 

Papabravo

Joined Feb 24, 2006
21,159
Your block diagram is incomplete. It does not show the pathway from the ALU (Arithmetic Logic Unit) to memory. It also does not show how a write from a register to memory occurs. There are at least two possibilities for how this might happen.
 

Thread Starter

CNC682

Joined Jan 23, 2015
27
Ok, Well it says using the data sheet to answer both questions but it says refer to that block diagram. So what are two possibilities and types of addressing modes?

Ithink it uses fetch code and exceute method
 
Last edited:

Papabravo

Joined Feb 24, 2006
21,159
Method #1 is to add ACC.A and ACC.B in the ALU and rout the low byte of the result to the data port (aka DATA[7:0]) with the address bus (not shown) containing the memory address from the instruction or from a register(not shown).
Method#2 is to add ACC.A and ACC.B and put the result in ACC.D, then run a separate cycle to store ACC.D in memory via the address bus(not shown) and the data port.

In the block diagram the Address Logic can only accept data from the PC or the stack pointer. That's complete BS.
 

Thread Starter

CNC682

Joined Jan 23, 2015
27
There are 6 types of addressing modes on the data sheet. Which one applies to both methods ideally, the explanations of them are not clear?

Immediate
Direct
Extended
Indexed
Inherent
Relative

What about the index registers? Do they contain addresses?
 
Last edited:

Thread Starter

CNC682

Joined Jan 23, 2015
27
Ok thanks, I know the block diagram is not ideal as you have explained. Is my address range in hex (question 2 ) sound right or have I calculated it wrong?
 
Apologies for the bump. But it seemed more appropriate than reposting the question.

I am attempting this question and am baffled by question 1 and the data sheet.

This is what I've pieced together, so far:

ACC.A and ACC.B are accumulators: accumulator A and accumulator B respectively.

Accumulator A is the most significant octet while Accumulator B is the least significant octet.

These two general-purpose 8-bit accumulators are used to store operands and results of arithmetic calculations or data manipulations and then fed to the next immediate level, i.e. the contents of these two 8-bit accumulators are fed into the 16-bit ALU.

The order each octet is transmitted is: from Most Significant Octet to Least Significant Octet. [Is there a sequence of transfer?]

The binary operands are brought to the 16-bit ALU via two inputs from ACC.A and ACC.B via the address bus.

The addition takes place in the 16-bit ALU by adder circuits.

The result is stored in ACC.D (accumulator D).

Then a separate cycle is run to store ACC.D in memory via the address bus and data port, via the CCR, are stored in 16-bit Accumulator D.

The 16 bit index registers IX and IY are used for indexed addressing modes.

The addressing modes that would be employed in this addition are: Direct, Extended, Indexed

However, I feel this is not enough. Do they want more?

For example, the role of the condition code register (CCR) which contains five status indicators (carry, overflow, zero, negative, and the half carry flag), two interrupt masking bits (IRQ and XIRQ mask), and a STOP disable bit.
Also, the role of the stack and the stack pointer in the process.

Thank you for you patience.
 
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