Hi Everybody,

I've been playing with a coolrunner II test kit and thought I'd try doing some coding in VHDL. As my first little experiment to get used to VHDL I figured that I should make an LED blink...

Long story short, I can get the board to turn the LED on and off (not a difficult task), however I am trying to generate a clock that will turn it on and off at 1 Hz. However when I flash the following code, it appears that I always get 50% duty cycle at the same frequency regardless if I tell the clock to have a 100 second period or 1 nano-second period. Any help?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blink is
    Port (A : in std_logic; --A not used currently...
            B: out std_logic);
end blink;

architecture blinker of blink is
             --set up state machine variables
	type state_type is (st0, st1);
	signal ps, ns : state_type;
	signal ck : std_logic := '0';
	
begin
             --setup clock
	clk : process
	begin
	ck <= not ck after 1000 ms;
	end process clk;
	
             --go to next state on next clock cycle
	sync_proc : process(ns, ck)
	begin
		if (rising_edge(ck)) then 
			ps <= ns;
		end if;
	end process sync_proc;
	
             -- machine
	proc : process(ps)
	begin
		case ps is
			when st0 =>
				ns <= st1;
			when st1 =>
				ns <= st0;
			when others =>
				ns <= st0;
		end case;
	end process proc;
	
             --output
	with ps select
		B <= '0' when st0,
		       '1' when st1,
		       '0' when others;
	
end blinker;

 

You might be absorbing the clocks. Try

ck <= transport not ck after 1000 ms;

But the real issue here is that you can't separate learning any HDL without also learning how to simulate. I can't stress this enough, because coding is fun but simulation is usually not. (You'll be doing more of the latter than the former - it's how you trace down problems just like yours.) Xilinx usually includes one or more trial simulators with their kits. Otherwise you may want to download the free ISE WebPack from the Xilinx site.