Couple question

Thread Starter

Tigerlui

Joined May 9, 2009
3
Noise margin is
a. a measure of the ability of a logic gate to drive further logic gates.
b. the time required for a signal to travel from the imput of a logic gate to the output.
c. the difference between what a logic gate outputs as a vaild logic voltage and what the input of the next gates expects to see as a valid logic voltage.
d. the difference in chip temperature from when the power is off to when the power is on.

I think it's c. but im not sure.

When you compare TTL logic gates to CMOS gates, the CMOS gates have an advantage of having___.
a. higher power consumption.
b. lower propagation delay.
c. less sensitivity to static electricity.
d. lower power consumption.

What is the minimum number of flip flops needed to build a mod 12 synchronous counter?
a.2
b.3
c.4
d.5

How many flip-flops are required to implement a divide-by-16 circuit?
a.4
b.3
c.2
d.1

And how to identify a devices is a negative edge triggered D flip-flop?

Anyone can help me or tell me the answers? Or any website i can find the answers? please
 
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