As a teaching exercise, I have tasked my students to design a digital clock using all discrete transistors, no modern IC's or MCU's allowed.
Part of the exercise is the "open design process" - collecting the best ideas and solutions from everywhere.
To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.
One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.
Attached is my rough design of a single stage Flip-Flop, with inputs that can be connected up to create a synchronous counter.
The circuit is basically a single flip flop with 2 each 3 input NAND gates to steer and control the counting.
Any simpler ideas?
Part of the exercise is the "open design process" - collecting the best ideas and solutions from everywhere.
To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.
One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.
Attached is my rough design of a single stage Flip-Flop, with inputs that can be connected up to create a synchronous counter.
The circuit is basically a single flip flop with 2 each 3 input NAND gates to steer and control the counting.
Any simpler ideas?
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