Of the various Wierdo clock designs on the innergoogle. the transistor clock cited by Bertus is my second favorite. First is an all-analog digital clock. Lotsa transistors and opamps, zero traditional digital logic. As you suggest, it uses a switched current source, capacitor, and comparator for a decade counter stage. Overall, pretty compact.There is another approach called the step divider or stairway counter, or something like that.
It;s a divide by 5 in series with a divide by 10. for 1 pps.
It;s a divide by 6 in series with a divide by 10 for 1 pp minute.
Looks a bit OTT to me - should be able to do it with 2 diodes and a couple of loading capacitors. Pretty sure there's a design drifting about the WWW somewhere.As a teaching exercise, I have tasked my students to design a digital clock using all discrete transistors, no modern IC's or MCU's allowed.
Part of the exercise is the "open design process" - collecting the best ideas and solutions from everywhere.
To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.
One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.
Attached is my rough design of a single stage Flip-Flop, with inputs that can be connected up to create a synchronous counter.
The circuit is basically a single flip flop with 2 each 3 input NAND gates to steer and control the counting.
Any simpler ideas?
Are you planning for each student to build a clock? Or doing it as a class project?Ok now we will go back into the cave for a while and see what we come up with.
I am also intrigued by this notion, but the main concern is that it could drift off and start missing a count.I have been toying with the idea of an analog step counter first suggested by @MisterBill2 back in post #6.
Have a constant current source charge a capacitor at about 60mV per step. After 50 steps, reset the capacitor when it reaches 3000mV.
You can do the similar procedure after 60 steps for the 60-second counter, i.e. reset after 3600mV.
Exactly correct about losing a step or two. THAT is the reason for 2 stages and fewer stops. That is how frequency division was done before FFs were invented. so you will need to look in some older reference books.I am also intrigued by this notion, but the main concern is that it could drift off and start missing a count.
Cascading these might be one answer, if it only divides by 10, it would be less sensitive to drift.
The whole class builds one clock.
The stairstep divider in this link shows exactly the principle that I was referring to, and doing it with inverters is a much simpler way to do it. But for divide by 50 I would factor that into 2, 5, and 5, for more stable operation and much larger steps.Here is an interesting compilation of non-traditional ideas for frequency division.
The "injection locked oscillator" is especially interesting.
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