Counter Circuits for All-Transistor Digital Clock

AnalogKid

Joined Aug 1, 2013
8,154
There is another approach called the step divider or stairway counter, or something like that.
Of the various Wierdo clock designs on the innergoogle. the transistor clock cited by Bertus is my second favorite. First is an all-analog digital clock. Lotsa transistors and opamps, zero traditional digital logic. As you suggest, it uses a switched current source, capacitor, and comparator for a decade counter stage. Overall, pretty compact.

ak
 

AnalogKid

Joined Aug 1, 2013
8,154
What?

It;s a divide by 5 in series with a divide by 10. for 1 pps.
It;s a divide by 6 in series with a divide by 10 for 1 pp minute.
Exactly:
divide-by-5 = 3 flipflops
divide-by-10 = 4 flipflops
divide-by-6 = 3 flipflops
divide-by-10 = 4 flipflops

total = 14 flipflops. This is to be expected because of the relatively inefficient divide ratios. A 12-stage binary divider with 7 diodes to decode 3000 will take many fewer parts.
 

ian field

Joined Oct 27, 2012
6,539
As a teaching exercise, I have tasked my students to design a digital clock using all discrete transistors, no modern IC's or MCU's allowed.
Part of the exercise is the "open design process" - collecting the best ideas and solutions from everywhere.

To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.

One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.

Attached is my rough design of a single stage Flip-Flop, with inputs that can be connected up to create a synchronous counter.
The circuit is basically a single flip flop with 2 each 3 input NAND gates to steer and control the counting.

Any simpler ideas?
Looks a bit OTT to me - should be able to do it with 2 diodes and a couple of loading capacitors. Pretty sure there's a design drifting about the WWW somewhere.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,454
Ok now we will go back into the cave for a while and see what we come up with.

Thanks all for the stimulating input!
 

dl324

Joined Mar 30, 2015
9,151
Ok now we will go back into the cave for a while and see what we come up with.
Are you planning for each student to build a clock? Or doing it as a class project?

As a class project it wouldn't be that much work; depending on how many students you have. Only 4 or 5 different counters and one decoder; each with one or more copies. Groups could breadboard/prototype their parts and then connect them together to make a complete clock.

The decoder for my LED matrix took 58 gates, so I'm using multiplexers (5 gates each times 4) instead of replicating the decoder logic.
 

MrChips

Joined Oct 2, 2009
19,421
I have been toying with the idea of an analog step counter first suggested by @MisterBill2 back in post #6.

Have a constant current source charge a capacitor at about 60mV per step. After 50 steps, reset the capacitor when it reaches 3000mV.
You can do the similar procedure after 60 steps for the 60-second counter, i.e. reset after 3600mV.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,454
I have been toying with the idea of an analog step counter first suggested by @MisterBill2 back in post #6.

Have a constant current source charge a capacitor at about 60mV per step. After 50 steps, reset the capacitor when it reaches 3000mV.
You can do the similar procedure after 60 steps for the 60-second counter, i.e. reset after 3600mV.
I am also intrigued by this notion, but the main concern is that it could drift off and start missing a count.
Cascading these might be one answer, if it only divides by 10, it would be less sensitive to drift.

The whole class builds one clock.
 

MisterBill2

Joined Jan 23, 2018
4,055
I am also intrigued by this notion, but the main concern is that it could drift off and start missing a count.
Cascading these might be one answer, if it only divides by 10, it would be less sensitive to drift.

The whole class builds one clock.
Exactly correct about losing a step or two. THAT is the reason for 2 stages and fewer stops. That is how frequency division was done before FFs were invented. so you will need to look in some older reference books.
 

MisterBill2

Joined Jan 23, 2018
4,055
Here is an interesting compilation of non-traditional ideas for frequency division.

The "injection locked oscillator" is especially interesting.
The stairstep divider in this link shows exactly the principle that I was referring to, and doing it with inverters is a much simpler way to do it. But for divide by 50 I would factor that into 2, 5, and 5, for more stable operation and much larger steps.
 

AnalogKid

Joined Aug 1, 2013
8,154
Grabbed this image off the innergoogle for illustration:


If the bottom of R2 is lifted from GND and driven with a clock, and the load is a low dissipation capacitor, then you have a stepped ramp output to feed to a comparator. Add a resistor from the base to Vcc to assure rapid turn off.

ak
 

Bernard

Joined Aug 7, 2008
5,291
Can a 2N6028, PUT, be considered a transistor for this clock? If so need about 5 using @MisterBill's
approach in post #6. Divide by 5-3 stages, divide by 6 & 4 one stage each. Might need a non inverting amp. every other stage?
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,454
Working on the stair-step frequency divider concept now.

This is my first cut at the design, works well, but I would not use it for divide ratios of more than 10.
One element needs to be adjustable, so you can "tune" the injected current so it centers on the desired divide ratio.

Requiring 6 transistors, it's far simpler than the equivalent flip flop design, which requires 4 flip flops, containing 4 transistor each, for a total of 16 active devices, and a ton of resistors.

For low frequency operation, The caps should be bigger to compensate for leakage drift.
Will buy some large polyester caps to try next.
Pump_divider.png
 

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Thread Starter

Sensacell

Joined Jun 19, 2012
2,454
Pump_Divider.JPG

Here is an update on the progress- this is the 50Hz signal processing board, (low-pass and Schmitt trigger) and the divide-by-3000 board that outputs one pulse per minute.
The divider is 4 stages: divide by 10, (5 Hz) divide by 10, (0.5 Hz) divide by 10, (20 seconds per pulse) and the final divide by 3, to get one pulse per minute.

Each stage uses a pulsed current source to generate a staircase waveform that then triggers a threshold circuit to discharge the capacitor.
A trimmer adjusts the current sources to calibrate the division ratio of each stage.
We had an interesting time dealing with leakage currents, they caused the voltage on the capacitor to drift more than expected, this was finally traced to flux contamination. A thorough cleaning with IPA fixed the problem.

Pretty cool to get divide-by-3000 with only 14 transistors.

Students are now fabricating the ring counters.
 

MisterBill2

Joined Jan 23, 2018
4,055
The education about the leakage was probably just as valuable as the other parts of the lesson. And I am glad that the staircase method is working out well. Can you imagine doing the whole system using triode vacuum tubes? That is how things were done for many years, before transistors.
 
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