Counter Circuits for All-Transistor Digital Clock

Thread Starter

Sensacell

Joined Jun 19, 2012
2,452
As a teaching exercise, I have tasked my students to design a digital clock using all discrete transistors, no modern IC's or MCU's allowed.
Part of the exercise is the "open design process" - collecting the best ideas and solutions from everywhere.

To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.

One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.

Attached is my rough design of a single stage Flip-Flop, with inputs that can be connected up to create a synchronous counter.
The circuit is basically a single flip flop with 2 each 3 input NAND gates to steer and control the counting.

Any simpler ideas?
 

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WBahn

Joined Mar 31, 2012
24,854
Have you counted up how many transistors, diodes, and resistors you are going to need not only to get the clock division you need, but to store the data you need keep the time and the glue logic to make everything tick? Seems like you are going to need at least a couple dozen flip flops, making it somewhere around 500 resistors just for that.

Are you sure that this is the most effective use of their time and energy?

How about having them implement the basic building blocks using discrete components once or twice -- say build two of these flip flops and demonstrate that they work as advertised when connected together is a simple state machine -- and after that they get to use modern DFF chips. Same with the basic logic gates. Then have them build a small counter using DFF chips and, after that, they get to use a comparable counter IC.

That way they get their hands dirty in the fundamentals enough to make the ICs understandable and not just magic, but don't spend all their time after that has been accomplished slogging through the drudgery (and inevitable messups and loose connections and burned components) that teaches them little beyond why you never want to actually do something this way unless you simply have no choice.
 

Yaakov

Joined Jan 27, 2019
1,604
Is the mains frequency actually reliable enough, I got the impression it can vary slightly?
The mains frequency is necessarily held within very narrow range (~±.2 Hz) because the generators must stay synchronized. Larger deviations can cause physical damage to the generators.

However, even with the smallish error band, the resulting timekeeping by a mains-driven clock is not as accurate as that because of phase differences.

Here’s a nice little paper explaining it: https://wwwhome.ewi.utwente.nl/~ptdeboer/misc/mains.html
 

MisterBill2

Joined Jan 23, 2018
4,055
As a teaching exercise, I have tasked my students to design a digital clock using all discrete transistors, no modern IC's or MCU's allowed.
Part of the exercise is the "open design process" - collecting the best ideas and solutions from everywhere.

To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.

One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.

Attached is my rough design of a single stage Flip-Flop, with inputs that can be connected up to create a synchronous counter.
The circuit is basically a single flip flop with 2 each 3 input NAND gates to steer and control the counting.

Any simpler ideas?
There is another approach called the step divider or stairway counter, or something like that. Each input pulse adds an increment to an analog voltage, and at some level it triggers an output pulse. you only need 3 stages, 5 steps, 5 steps, and 2 steps, to divide by 50. Many of the early versions used tubes, but I have seen solid state versions. And it does look like a stairway on a scope display.
 

MisterBill2

Joined Jan 23, 2018
4,055
For the ring counters you can use 2 sections, divide by 6 and then divide by 10, each stage of the divide by 6 enables one group of ten indicators, such as LEDs. It allows you to reduce the number of wires and also the number of stages, and eliminates the decoding logic. So it saves a whole lot of parts. But it would work for a circular clock, not a digital one. More display elements but discrete LEDs are cheaper than 7-segment displays, at least in the larger sizes.

Also, a circular clock is more fun to watch, and far less complex of a circuit. All of those flipflops and decoders can be very tedious.
 

MisterBill2

Joined Jan 23, 2018
4,055
If the line frequency is any issue there are also crystal oscillator circuits and staircase dividers to get down to much lower frequencies. But normally the mains frequency is good enough for clocks.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,452
That transistor clock was a partial inspiration for the project, it's great to have a point of departure for design improvements.

We are doing our own variation on the design, trying to come up with some clever simplifications.

The intention is twofold: Teach about transistors and introduce logic circuits, while also teaching the meta-lessons learned from the "slog and drudgery" - learning to think-through a complex, real world project. Nobody teaches kids how to build real stuff anymore, this skill is very important if you want to be able to create and innovate.

How to develop and implement the smartest prototyping strategy to reach the goal as quickly as possible, at minimum cost.
How to build and assemble a prototype in a modular way to ease test and debugging in the development process.
How to build reliable prototype electronics, with reliable connections and sound physical structures.

The project is difficult and large enough that seemingly small strategic decisions can have a large impact.
I believe this exercise will help students think deeper and wider when approaching problems.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,452
For the ring counters you can use 2 sections, divide by 6 and then divide by 10, each stage of the divide by 6 enables one group of ten indicators, such as LEDs. It allows you to reduce the number of wires and also the number of stages, and eliminates the decoding logic. So it saves a whole lot of parts. But it would work for a circular clock, not a digital one. More display elements but discrete LEDs are cheaper than 7-segment displays, at least in the larger sizes.

Also, a circular clock is more fun to watch, and far less complex of a circuit. All of those flipflops and decoders can be very tedious.
Current plan is to make 7 segment displays out of 60V LED filaments ripped from some LED light bulbs, only 700 uA / segment actually looks great!.
Since this thing is going to be large, the display should not be dwarfed by the guts!

Using the decade ring counter and a diode matrix to drive the segments eliminates all the decoding from the binary counter design shown in the original clock schematic, some part savings there.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,452
There is another approach called the step divider or stairway counter, or something like that. Each input pulse adds an increment to an analog voltage, and at some level it triggers an output pulse. you only need 3 stages, 5 steps, 5 steps, and 2 steps, to divide by 50. Many of the early versions used tubes, but I have seen solid state versions. And it does look like a stairway on a scope display.
Ahh cool idea!! like a charge pump stair step circuit and some comparitors.

I need to divide down to 1 pulse per minute, divide by 3000, so that's a tough nut for analog!
Maybe it could be done with cascaded divide by 10 circuits and one divide by 3.
 

MisterBill2

Joined Jan 23, 2018
4,055
I did not have any success lighting those fake filament things from a failed LED bulb. I never got as high as 60 volts, though. Decoding off the ring counter does make sense, but the stair step uses even fewer parts than a ring counter. And there would be some analog learning as well, in addition to learning to deal with component tolerances.
Please share the design with us when the project is completed, not just for us, but then the students will have their work published, which looks good on a resume, or a transcript.
 
ne tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute? This requires a division ratio of 3000.
Looking now at cascading multiple transistor flip-flops, still we need at least 12 stages of flip flops, which ends up being a ton of parts.
What?

It;s a divide by 5 in series with a divide by 10. for 1 pps.
It;s a divide by 6 in series with a divide by 10 for 1 pp minute.

Divide by N counter: http://www.wenzel.com/wp-content/uploads/161divdr.pdf

get started using a 1pps oscillator and then design the front-end using line frequency together. During the development, there is no mains anywhere.

==

Over the LONG term line frequency is corrected. Over the short term it pretty good.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,452
The LED filaments we have are made from 18 white LED's in series, they try to impedance match the strips to mains - somewhat.
The bulb we salvaged them from had 4 "filaments" with 18 LED's in series, for a total Vf of 220 VDC! (55V per filament)

We'll drive our LED's from a transformer-derived 65 VDC, with a current sink running about 700 uA per segment to get a nice warm glow.
 

Thread Starter

Sensacell

Joined Jun 19, 2012
2,452
What?

It;s a divide by 5 in series with a divide by 10. for 1 pps.
It;s a divide by 6 in series with a divide by 10 for 1 pp minute.

Divide by N counter: http://www.wenzel.com/wp-content/uploads/161divdr.pdf

get started using a 1pps oscillator and then design the front-end using line frequency together. During the development, there is no mains anywhere.

==

Over the LONG term line frequency is corrected. Over the short term it pretty good.
1 pulse-per minute is 1/60th of 1 Hz, or .0166666 Hz.

50 Hz / 6 = 8.333 Hz. ----- divide by 10 is 0.833 Hz??
 
@sensacel @dl234 Migraine. Damn. Sorry. The divide by n counter was the concept. I don't think I messed up the math.

That's why I put the wrong stuff in the fridge. One migraine sufferer put money in a parking meter and was waiting for the bubble gum to come out.

reading it over with a migraine. I think I'm right

(60 times in 1 second / 60)is 1 time in 1 second or 1 PPS (60=6*10)
60/6 = 10; 10/10 = 1 pps

then you get 1 pulse per 10s and finally one pulse per minute.

Make sure units cancel.
 
Last edited:

sghioto

Joined Dec 31, 2017
1,038
One tricky problem is how to divide our mains frequency of 50 Hz (in Asia) down to one-pulse-per-minute?
Why not just design your own clock generator if this is mainly an exercise. As you said:
"We are doing our own variation on the design, trying to come up with some clever simplifications."
SG
 

dl324

Joined Mar 30, 2015
9,150
To keep it reasonably simple, we are shooting for a simple 4 digit clock: HH:MM display.
We plan to use decade ring counters for each digit, with diode matrix decoding for the seven segment displays.
I saw a clock using no IC's and no board. I liked the look of it and decided to build one of my own. This particular design decided to obscure functional blocks. For mine, I plan to group by logic blocks. Still thinking about jigs to help with assembly.

I chose to do synchronous counters with R#S# flip flops and use 4 5x7 discrete LED matrices to display hours and minutes. Seconds will be a ring of 60 LEDs arranged in a circle around the LED matrices.

The flip flop uses 2 transistors, 6 resistors, 4 diodes, and 2 capacitors. I decided to forego the complexity of reset. If your supply voltage is sufficiently high, you'll want to add diodes anti-parallel to the base-emitter junctions to prevent them from breaking down.

I tried using diode logic for OR and AND, but soon abandoned that idea and am trying to use DTL NAND as much as possible. I've prototyped the hours and 10's minutes logic and designed the LED matrix decode logic yesterday. I plan to multiplex the display because I don't want to duplicate the decode logic.

I experienced a problem with output loading and the clock. I reduced the voltage swing on the clock pulses to give me some margin. I'm just using a couple LEDs to drop the voltage now and will look for something more elegant later.
 
Last edited:

MisterBill2

Joined Jan 23, 2018
4,055
The LED filaments we have are made from 18 white LED's in series, they try to impedance match the strips to mains - somewhat.
The bulb we salvaged them from had 4 "filaments" with 18 LED's in series, for a total Vf of 220 VDC! (55V per filament)

We'll drive our LED's from a transformer-derived 65 VDC, with a current sink running about 700 uA per segment to get a nice warm glow.
65 volts times 700 MICRO amps is 45 MILLIWATTS. So I am guessing that there may be a slight error some place.
 
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