Hi,

I have attached a file related to the output waveform of a CCD sensor. I am working with one right now and I have a similar waveform, the TCD1209DG to be exact. The signal floats on top of a 5v DC offset and it has a frequency of 12.5MHz, as it follows the phi 1 and phi 2 sampling clocks.

The time at which the output signal is visible, is approximately 30ns. The time at which the reference signal is visible is also approximately 30ns. I would like to introduce correlated double sampling, it however need a very fast switch with pretty fast rise times. In order to isolate the two signals in its respective capacitor. I have looked at MOSFETS with MOSFET drivers, analog switches, etc. But they're not fast enough or draw too much current from the CCD output when connect to the CCD output. I used LTSpice and Microcap-12 to simulate this.

I'd be happy to hear if anybody has suggestions on how to introduce fast switches with around 10ns rise time, or how to process this CCD output signal.

 

Power supply has a limit of 200+- mA and can deliver max 15v

 

I think we used a sample and hold circuit driven from the clock. The sample and hold sees the signal in the 30nS window and is blind to the rest of the time.

 

Thanks for the reply

I'm having trouble understanding the response, do you mean that you just sample and hold the output level in the 30 nanosecond window. Then waiting for the next pixel, doing the same thing over while not sample and holding the reference level?

This would mean that my timing constraints would be much less as i would only have to time the output level. However, I would still have white and kTC noise. Are you suggesting that you didn't implement correlated double sampling in your system?

 

CDS is good for removing KTC reset noise, but it's difficult to do externally for a 30nS window.
CCDs often have internal circuitry to do that.
External S/H for that short a period is problematic.
Sorry but I don't have any good suggestions for doing that.

 

Thats not a problem, I already had the same suspicion. I think i will just process the ccd output without correlated double sampling then.

First eliminating the DC offset, by feeding the signal to a differential amplifier. I will subtract it so that the signal will be low enough so that an ADC converter can read it. Also amplifying the signal so the ADC converter can read it more easily.

any thoughts on that?

 

Also amplifying the signal so the ADC converter can read it more easily.

any thoughts on that?

You are sampling the 30ns signal?

 

Yes, i will just feed the whole signal(80ns period) to an ADC converter and use a clock from my FPGA to exactly time the 30ns output signal

 

Yes, i will just feed the whole signal(80ns period) to an ADC converter and use a clock from my FPGA to exactly time the 30ns output signal

If you A/D converter is fast enough to capture the reset volage also, then you can subtract it digitally from the signal to do the CDS.

 

I think i can experiment that way, i’ll try to find an ADC that is fast enough. Otherwise, the correlated double sampling issue in the system is not really a big issue.