converting power supply signal into pulse signal

Thread Starter

yef smith

Joined Aug 2, 2020
1,447
Hello , I have a power supply which outputs +12V -12V as shown below in the CSV csources and plots.I get stable 12V -12V after a second
Is there a way to take the voltage after its being stable and make a pulse as shown below(or close to it) after 5seconds or so?(automatickly without using MCU)
Or atleast when the "device recognises we have 12V and -12V stable then it releases them at once(not like the power suplly does it)?
Thanks.

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Alec_t

Joined Sep 17, 2013
15,105
If the -V always becomes stable a bit later than the +V you could integrate the -V and operate a 2-pole (electronic) switch when the integral reaches some threshold value. Or simply use a time-delay relay.
 
With 4 optocouplers:

Both left Leds has to be supplied (input voltages above 11V) to both right Leds become switched on simultanously (using And gate) , and thus the output power transistors become switched on at the same time.

IMG_1112.jpeg
Note: It´s a good manner to use a two schmitt triggers instead of left input transistors, ortherwise if Vin voltages contain ripple the outputs will bounce few times (but both together).
 
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AnalogKid

Joined Aug 1, 2013
12,050
Something like this?
Q2 needs a turn-off resistor similar to R3.

Also, the circuit assumes that if the +12V supply is at least +3 V, both supplies must be +/-12 V. This may or may not be ok with the TS, because there are several fault conditions where this is not valid.

ak
 

Alec_t

Joined Sep 17, 2013
15,105
Q2 needs a turn-off resistor similar to R3.
Indeed it does. It was intended, but got overlooked.
Also, the circuit assumes that if the +12V supply is at least +3 V, both supplies must be +/-12 V.
Not quite so. The Schmitt's supply rises with Vdd but the Schmitt isn't triggered until the cap voltage rises to about +7V half Vdd, which occurs at about 3 sec (adjustable by varying the R1C1 time constant), i.e well after both rails have stabilised.

Edit:
If there is any chance that one rail failed to stabilise, then the circuit would be better if modified to monitor both rails.
 
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AnalogKid

Joined Aug 1, 2013
12,050
If the +12 V output rises only to +5 V (or even +3 V), the gate will function normally and its output will go low after the R-C delay. Thus, both outputs can be enabled when the input voltages are as low as +5 V and 0 V.

The Schmitt threshold voltage is mostly a percentage of Vdd, so the time delay should be approx the same for any Vdd from 3 V to 15 V.

At Vdd = 10 V, the typical VT+ is 6.8 V. This is 68% of Vdd, which is greater than the one-time-constant value of 63%. At Vdd = 12 V, the delay period will be approx. 1.3 x R x C.

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Fairchild Semiconductor, September, 2003 / National Semiconductor, October, 1987

ak
 
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Thread Starter

yef smith

Joined Aug 2, 2020
1,447
Hello,The problem I see with the shmidt trigger needs a supply voltage.
My only DC voltage is the input +12 and -12 which are not stable.
What could be done?

Also the simulation file doesnt have PNP npn and shmidt trigger model are missing, i cannot run the simulation,could you please update them?

Thanks.

https://www.ti.com/product/CD40106B#design-development
 
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AnalogKid

Joined Aug 1, 2013
12,050
Hello,The problem I see with the shmidt trigger needs a supply voltage.
My only DC voltage is the input +12 and -12 which are not stable. What could be done?
You do not need a separate power supply for the logic chip. As long as the +12 V supply output is greater than +3.0 V, the 40106 can run off of it.

ak
 

Alec_t

Joined Sep 17, 2013
15,105
If the +12 V output rises only to +5 V (or even +3 V), the gate will function normally and its output will go low after the R-C delay. Thus, both outputs can be enabled when the input voltages are as low as +5 V and 0 V
Good point. The proposed circuit was intended only for the case where both supplies stabilise correctly at similar, but not necessarily identical, times.
 

Alec_t

Joined Sep 17, 2013
15,105
Here's another suggestion which takes on board the comments above and monitors both supply rails.
An LM393 could be used instead of the LT1716 dual comparator in the sim.
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The RC networks at the inverting and non-inverting inputs of the comparators ensure that one or other comparator ouput is low until both rails have reached within about 0.1V of their final value. These networks might need adjusting if there is significant ripple on the rails.
D1 is to prevent reverse breakdown of Q3 base-emitter junction. C5 is to reduce the chance of rail noise/ripple causing switch-off of the circuit outputs.

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Thread Starter

yef smith

Joined Aug 2, 2020
1,447
Hello Alec,I have tried to put a real BJT in the circuit the +12 pulse went well but the -12V did not pass when i used the MMBT222A model.Why this model is a bad choise for NPN?
LTspice is attached.
Thanks.


.MODEL DI_MMBT2222A NPN (IS=25.4f NF=1.00 BF=274 VAF=114
+ IKF=0.121 ISE=14.3p NE=2.00 BR=4.00 NR=1.00
+ VAR=24.0 IKR=0.300 RE=0.219 RB=0.877 RC=87.7m
+ XTB=1.5 CJE=27.6p VJE=1.10 MJE=0.500 CJC=14.2p VJC=0.300
+ MJC=0.300 TF=622p TR=124n EG=1.12 )

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crutschow

Joined Mar 14, 2008
38,325
The sim works if you don't use generic models for Q2 and Q3.

Never use generic diode or transistor models in LTspice as they can be flaky.

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Alec_t

Joined Sep 17, 2013
15,105
the -12V did not pass when i used the MMBT222A model.Why this model is a bad choise for NPN?
I think the model must have a problem. I tried many other models in the LTS standard npn library and they all performed well.

The sim works if you don't use generic models for Q2 and Q3.
Agreed. It also works with the generic models. I used those because the actual load which the rails will be driving is as yet unknown.
 

Thread Starter

yef smith

Joined Aug 2, 2020
1,447
Hello , the load is my sequencer circuit I have designed.
When i put NPN PNP models it worked great as shown in the DualSupplySwitch2_real_bjt file.
But when i connect the sequencer to this circuit then on the same spot I had -12V suddenly its -1V as shown below and in the attached zip file.
What could cause it?
Thanks.

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