Some examples show the SR having the Clock input??? S-R latches do not have a Clock input. Maybe this would be better. Clock has to be edge triggered, not shown in this example and might explain the S-R latch with a Clock input. So both examples are flawed I guess. Maybe you can't get to there in just a few gates.

 

(An older file). This is closer to what a J-K flip flop looks like on the inside. More than just adding a few gates.

 

The big difference between a SR and a JK is that the JK is a master-slave device. It actually contains two flip-flops, one clocked on the rising edge and one on the falling. Whereas the SR is basically a gated latch - level triggered not edge triggered.

 

The big difference between a SR and a JK is that the JK is a master-slave device. It actually contains two flip-flops, one clocked on the rising edge and one on the falling. Whereas the SR is basically a gated latch - level triggered not edge triggered.

Not all J-K are Master/slave types. Some are just edge triggered.

 

Not all J-K are Master/slave types. Some are just edge triggered.

Not really. JK flip-flops of non-master-slave types are level triggered. For edge triggering you need the master-slave type.
Non-master-slave JKs are almost impossible to work with, due to heavy restraints on setup and hold times.
Not relevant though, only the very early RTL/DTL/TTL flip-flops were non-master-slave. Today, you won't find them anywhere.

 

Re: " Today, you won't find them anywhere. "

Very true!. Mostly just found in the classroom.

 

Most actual implementations of flip flops use transmission gates to effect edge-triggered behavior. While there are two latches, they are not really in a master-slave configuration. Essentially they are two cross-coupled inverters and one phase of the clock they are holding their data and on the other they are being overdriven by their input. When the clock is LO, the first stage accepts data from the input but has it's feedback path disabled as well as the path to the output stage. The output stage, on the other hand, is holding the data. On the rising edge of the clock, the first stage is disconnected from the input and placed in a holding state while the output latch is turned transparent by connecting the output of the first stage to its input and disabling the feedback path. This involves race conditions, but since the design has complete control over them they can ensure that they are resolved properly. Since the inputs to the whole thing are disconnected from the first stage, the whole circuit appears to be edge sensitive and, unlike a classic master-slave topology, the input is transferred to the output on the rising edge as well. On the falling edge of the clock the output stage's feedback path is enabled and the input is disconnected, while the input stage's feedback back is disabled and the input is reconnected. Again, this involved critical races that the designer must ensure will be resolved properly.

 

Whether you call it "input stage" and "output stage" or "master" and "slave", the result is the same. And using "transmission gates" is just something that is a very useful technique CMOS circuits.
But who cares. Name someone who'll build her/his own JK flip-flop.

 

View attachment 109334
Some examples show the SR having the Clock input??? S-R latches do not have a Clock input. Maybe this would be better. Clock has to be edge triggered, not shown in this example and might explain the S-R latch with a Clock input. So both examples are flawed I guess. Maybe you can't get to there in just a few gates.

Why do you think this example is flawed? Simply start with an assumed state, such as Q=0 and Q'=1, and then apply some J,K signals and track the state of all the signals. You should see that it behaves as an edge-triggered JKFF. To see the effect of the propagating signals better, assign a one unit propagation delay to each gate. To see it even better, replace the SR latch with a pair of cross-coupled NAND gates.

 

Whether you call it "input stage" and "output stage" or "master" and "slave", the result is the same. And using "transmission gates" is just something that is a very useful technique CMOS circuits.
But who cares. Name someone who'll build her/his own JK flip-flop.

Well, since I used to design mixed-signal CMOS ASICs, I guess I would have to name myself.

Plus, many students implement the basic building blocks as discrete circuits so that they understand how they work when they use ICs at the next stage of their education. I think that's a much better approach than the "here's a bunch of magic blocks for you to use" approach that is becoming increasingly common.

 

Not really. JK flip-flops of non-master-slave types are level triggered. For edge triggering you need the master-slave type.
Non-master-slave JKs are almost impossible to work with, due to heavy restraints on setup and hold times.
Not relevant though, only the very early RTL/DTL/TTL flip-flops were non-master-slave. Today, you won't find them anywhere.

You must be thinking of long ago - I can't remember ever having seen a non-master/slave JK.

Usually the whole point of a JK is you can set up the input flipflop before clocking it through to the output flipflop - although that discipline is more refined with D type.

My first job was with 930 series DTL - I'd have to search around for the datasheets to remind me what their JKs were like - but I vaguely remember them being 2 stage.

 

Well, since I used to design mixed-signal CMOS ASICs, I guess I would have to name myself.

The operative phrase here is "used to". I've also designed ASICs, but nowadays macros or complete logic elements such as JKs are used directly in a design.

On your comment on education, my opinion is "perhaps".
I do not see a need for students to design their own JK flip-flop, as they will never have to do this in practice. The functionality of different logic elements, be it gates, latches and FFs is much more useful, and gives far more insights into even more complex circuits (counters, shift registers and other)

You must be thinking of long ago - I can't remember ever having seen a non-master/slave JK.

The Texas Instruments TTL databook from the late 70s or early 80s (in hard cover, and highly coveted by owners) specifically mentions if an FF is master-slave or not.
Additionally, my digital design bible from that time (William I. Fletcher, "An Engineering Approach to Digital Design") specifically warns students about the pitfalls of non-master-slave designs.
I still have the book and often use it as reference.

I suppose that is long ago... sigh.

 

Why do you think this example is flawed? Simply start with an assumed state, such as Q=0 and Q'=1, and then apply some J,K signals and track the state of all the signals. You should see that it behaves as an edge-triggered JKFF. To see the effect of the propagating signals better, assign a one unit propagation delay to each gate. To see it even better, replace the SR latch with a pair of cross-coupled NAND gates.

you mean the one with the S-R latch with a Clock input? S-R latches do not h

The operative phrase here is "used to". I've also designed ASICs, but nowadays macros or complete logic elements such as JKs are used directly in a design.

On your comment on education, my opinion is "perhaps".
I do not see a need for students to design their own JK flip-flop, as they will never have to do this in practice. The functionality of different logic elements, be it gates, latches and FFs is much more useful, and gives far more insights into even more complex circuits (counters, shift registers and other)



The Texas Instruments TTL databook from the late 70s or early 80s (in hard cover, and highly coveted by owners) specifically mentions if an FF is master-slave or not.
Additionally, my digital design bible from that time (William I. Fletcher, "An Engineering Approach to Digital Design") specifically warns students about the pitfalls of non-master-slave designs.
I still have the book and often use it as reference.

I suppose that is long ago... sigh.

Ah, green with envy. TI put out some great books around that time. Yes, coveted is a good word.

 

The operative phrase here is "used to". I've also designed ASICs, but nowadays macros or complete logic elements such as JKs are used directly in a design.

On your comment on education, my opinion is "perhaps".
I do not see a need for students to design their own JK flip-flop, as they will never have to do this in practice. The functionality of different logic elements, be it gates, latches and FFs is much more useful, and gives far more insights into even more complex circuits (counters, shift registers and other)


.

Just about every useful permutation of flip flop has already been designed - its hardly worth re inventing the wheel.

Knowing what's in a flip flop and understanding what it does and how, is a whole 'nother thing.

 

The operative phrase here is "used to". I've also designed ASICs, but nowadays macros or complete logic elements such as JKs are used directly in a design.

The "used to" merely reflects the fact that I am no longer employed in that capacity, not that my former employer no longer designs flip flops. In point of fact, I still do consulting for them and one of those things often involves updating their standard library to a new process. Using the fab house's standard library is not an option for our designs because their libraries are virtually never sufficiently low-noise for our mixed-signal designs. So we designed our own implementations that are -- and also designed them so that they have a negative hold time -- and updating them to a new process involves understanding exactly how they work and what constitutes acceptable performance.

On your comment on education, my opinion is "perhaps".
I do not see a need for students to design their own JK flip-flop, as they will never have to do this in practice.

I hear the exact same thing said over and over about lots of things -- for instance, why should students learn to integrate something as they will never have to do this in practice?

The functionality of different logic elements, be it gates, latches and FFs is much more useful, and gives far more insights into even more complex circuits (counters, shift registers and other)

And understanding how basic CMOS gates work internally allows you to implement arbitrary logic using CMOS in a very direct manner instead of being limited to using potentially much larger logic-gate-level implementations.

And understanding how flip flops work internally allows you to design fundamental mode machines when they are called for. Today's technology increasingly needs to use asynchronous logic (and even completely clockless logic), and just knowing the functionality of latches and flip flops won't let you operate in that arena.

 

you mean the one with the S-R latch with a Clock input? S-R latches do not h

No. I mean the circuit he posted:



That S-R latch does not have any clock going to it. It is a classic pair of cross-coupled NAND gates.

 

WBahn, I'm not questioning your competence, and I'm certainly not interested in a "pissing contest" here. You are obviously passionately working in an area where you are an expert. But really, what you do applies to 0.001% of electronic students, which mean that their qualifications can be upgraded in a targeted way.

I hear the exact same thing said over and over about lots of things -- for instance, why should students learn to integrate something as they will never have to do this in practice?

I don't think I've ever said that

And understanding how basic CMOS gates work internally allows you to implement arbitrary logic using CMOS in a very direct manner instead of being limited to using potentially much larger logic-gate-level implementations.

And understanding how flip flops work internally allows you to design fundamental mode machines when they are called for. Today's technology increasingly needs to use asynchronous logic (and even completely clockless logic), and just knowing the functionality of latches and flip flops won't let you operate in that arena.

Again extremely specific to your area, but not relevant for the vast majority of students.

Benta.

 

I guess I'm just too old fashioned and want an engineer to understand the fundamentals instead of being little more than a monkey that searches lists of formulas or settles for letting the software do their thinking for them.

One example is the simple voltage divider. Most students have memorized a formula that they regurgitate and can use as long as the topology exactly matches the one the formula applies to (though they seldom realize that there even is this restriction). But ask them to design a voltage divider, given access to 0V, 2.5V and 3.3V supply rails, such that the output is at least 2.0 V when the input is 2.3 V and no more than 0.8 V when the input is 0.4 V and they are completely lost. They will flounder around aimlessly because they are only able to operate in monkey-mode and this problem requires that they actually understand the concepts covered in the first part of Circuits I.

I have interviewed dozens of applicants and most of them I give three problems (the above being one of them). I have only had one person that was able to come close to answering all three and, out of desperation, we have made job offers to most of the applicants that could reasonably answer any of them (which was fewer than one in ten). In all three cases applicants almost always throw out buzz words and stock, memorized formulas (making it clear that they have no understanding of either) and are simply incapable of analyzing or designing the simplest of non-stock circuits -- they are even incapable of recognizing that the circuit is non-stock to begin with.

 

WBahn, I understand what you are saying, and I agree to a large extent.
An applicant that can not even apply Kirchhoff mesh or node equations has a serious problem in circuit design. And if we talk analogue design, inability to use the complex symbolic method is even worse.
So yes, basic techniques are important.

But not necessarily down to knowing every gate of a part in a logic design. I find it valuable that semiconductor companies nowadays supply basically foolproof logic functions with well-defined parameters. I mean, do you really want to know the silicon doping-level of the power transistor that you are using?

Best Regards.

 

I guess I'm just too old fashioned and want an engineer to understand the fundamentals instead of being little more than a monkey that searches lists of formulas or settles for letting the software do their thinking for them.

One example is the simple voltage divider. Most students have memorized a formula that they regurgitate and can use as long as the topology exactly matches the one the formula applies to (though they seldom realize that there even is this restriction). But ask them to design a voltage divider, given access to 0V, 2.5V and 3.3V supply rails, such that the output is at least 2.0 V when the input is 2.3 V and no more than 0.8 V when the input is 0.4 V and they are completely lost. They will flounder around aimlessly because they are only able to operate in monkey-mode and this problem requires that they actually understand the concepts covered in the first part of Circuits I.

I have interviewed dozens of applicants and most of them I give three problems (the above being one of them). I have only had one person that was able to come close to answering all three and, out of desperation, we have made job offers to most of the applicants that could reasonably answer any of them (which was fewer than one in ten). In all three cases applicants almost always throw out buzz words and stock, memorized formulas (making it clear that they have no understanding of either) and are simply incapable of analyzing or designing the simplest of non-stock circuits -- they are even incapable of recognizing that the circuit is non-stock to begin with.

Bless you, good sir, for that one.