The ouput is a squarewave initiated by the falling
edge of the timebase signal but it is not a narrow pulse. See attached.

It looks like the timebase pulse width is similar to the output pulse width. Are you sure you are using and measuring the correct timebase signal?

 

The capacitor does not look like 100 nF to me.
If you have already changed the capacitor, try lower values.

 

Perhaps you have a bad IC.
Do have another you can try?

It's acting like the capacitor is shorted.

Post a picture of your latest circuit breadboard.

Here is the latest circuit breadboard. I will swap out the IC for another
as well as the capacitor later today.

 

The capacitor does not look like 100 nF to me.
If you have already changed the capacitor, try lower values.

The capacitor is 0.1uF. I will try lower values.

 

It looks like the timebase pulse width is similar to the output pulse width. Are you sure you are using and measuring the correct timebase signal?

Yes channel one and two appear to be identical. Channel 2 is 180 out of phase with channel one. The timebase signal is 1Khz.

It looks like the timebase pulse width is similar to the output pulse width. Are you sure you are using and measuring the correct timebase signal?

 

The capacitor is 0.1uF. I will try lower values.

Hello,

The capacitor will have to be low enough to be able to charge and discharge faster than the incoming half cycle time from the time base. If it is not low enough you will not see that narrow pulse. The capacitor value plays in with the resistor value that goes to VDD, which is labeled as "R1".

The idea with these kinds of circuits is that the cap discharges during one half cycle of the input so that when the input changes state the cap provides a quick current pulse to the logic gate. The logic gate input therefore goes from a high to a low which changes the output state, and then once the cap charges up, the logic gate input again goes high, and that changes the output state back to the original state. When the input cycle changes again, the cap then discharges again which makes it ready for the next half cycle again.
If the cap cannot charge and discharge fast enough, the circuit will not work as expected.

 

Reduce that 100k to 1k. Leave the cap at 0.1u.

 

Reduce that 100k to 1k. Leave the cap at 0.1u.

I'd probably use a max of 0.01uf to keep the loading factor a bit lower along with a higher value resistor.

 

Reduce that 100k to 1k. Leave the cap at 0.1u.

Yes, I missed that a 1Hz clock was used in the sim, but a 1kHz clock in the actual circuit.

 

Pay attention to RC time-constant.
1 kHz clock is 1 ms. Half cycle is 500 μs. You want the RC time constant to be lower than this.
1 kΩ x 100 nF = 100 μs

 

Pay attention to RC time-constant.
1 kHz clock is 1 ms. Half cycle is 500 μs. You want the RC time constant to be lower than this.
1 kΩ x 100 nF = 100 μs

Hi crutschow and MrChips:

Sorry. My scope will not measure a frequency below 10 hz so the sim uses 2hz (which is the
frequency that I really want) and I am using 1Khz to test the breadboard circuit. Now I realize
that the RC time constant is an issue. Not sure what to do. I figured that with a 1Khz timebase
I could see on the scope that the circuit works but then I won't know if it works with a 2 Hz
timebase.

 

Two points to note.

1) Your oscilloscope works below 1 Hz as I have already explained in another thread.

2) If your RC circuit works at 1 kHz it will also work at 1 Hz without modification. The reverse is not necessarily true. In other words, you need the RC time-constant to be about 5 times lower than the clock period.

 

Hello,

The capacitor will have to be low enough to be able to charge and discharge faster than the incoming half cycle time from the time base. If it is not low enough you will not see that narrow pulse. The capacitor value plays in with the resistor value that goes to VDD, which is labeled as "R1".

The idea with these kinds of circuits is that the cap discharges during one half cycle of the input so that when the input changes state the cap provides a quick current pulse to the logic gate. The logic gate input therefore goes from a high to a low which changes the output state, and then once the cap charges up, the logic gate input again goes high, and that changes the output state back to the original state. When the input cycle changes again, the cap then discharges again which makes it ready for the next half cycle again.
If the cap cannot charge and discharge fast enough, the circuit will not work as expected.

Thank you for the good explanation!

 

My scope will not measure a frequency below 10 hz

Of course it will.
A scope will measure DC up to its maximum frequency if you select the DC input.

The AC input just puts a capacitor in series to block any DC, so you can measure a small AC signal riding on a large DC level.
The capacitor acts like a high-pass filter which is what limits the low frequency response.

 

Of course it will.
A scope will measure DC up to its maximum frequency if you select the DC input.

The AC input just puts a capacitor in series to block any DC, so you can measure a small AC signal riding on a large DC level.
The capacitor acts like a high-pass filter which is what limits the low frequency response.

My circuit now consists of two 1K resistors and a 0.1uF disc cap.
I am feeding a 1Khz 5V pp square wave into it. I have also set
the inputs to DC as suggested. I am still not getting a narrow pulse
output. I also tried feeding a 2 Hz 5V pp square wave from the
function generator (since that is what the timebase will eventually do)
but the scope display just flashed off and on. I have attached an
image from the scope.

The second image shows what happens with a 2Hz timebase. In the top
right corner the display says f < 10Hz.

 

but the scope display just flashed off and on.

Did you adjust the trigger level to try to get a stable display?

This is my sim, which is what you should see at 1kHz:

 

Did you adjust the trigger level to try to get a stable display?

This is my sim, which is what you should see at 1kHz:

View attachment 333891

Here are my scope images feeding 2Hz timebase into the circuit.

 

Here are my scope images feeding 2Hz timebase into the circuit.

Looks like the capacitor is not in the circuit.

Post the signal at the output of the capacitor.
It should look like the red trace below for a 1kHz input.

 

Looks like the capacitor is not in the circuit.

Post the signal at the output of the capacitor.
It should look like the red trace below for a 1kHz input.

View attachment 333895

Here is my breadboard circuit result with 1Khz timebase which is what I was expecting to see. Channel 2
is the capacitor output.

When I use a 2Hz timebase channel 1 is a straight line that jumps up and down while channel 2 is a stationary straight line.

 

When you change the input signal from 1 kHz to 2Hz you need to change the TIM/DIV accordingly. You also need to change triggering to MANUAL.

Edit: If you were able to observe the output pulse correctly at 1 kHz input, you don’t have to change the TIM/DIV. Just change the triggering to MANUAL. Trigger on the falling edge of the input.