Hi,
I tried to learn a bit about logic gates and a simple question came to me. Can two NOT gates with connected outputs work as a NAND gate. Is it possible and what are advantages/disadvantages?

 

Not gate is not going to make a nand gate
this would

The not gate the emitter is tied to ground
the nand gate its emitter to collector then to ground.
There is no way to break the ground on the not gate of a ic.
But you could make the one in the pic if you wanted one to play with.

 

What kind of NOT gate are you talking about?

Let's consider a typical NOT gate, which actively asserts both output logic levels.

If you connect the outputs of two such NOT gates, what is the output if one input is HI and the other is LO?

Now, what if you use a single-ended output stage, meaning that it can only actively pull the output in one direction and things have to be passively pulled in the other? This is called wired logic.

Consider that if either input is LO, you want the output to be HI, independent of what the other input is. That means that you need each NOT gate to actively assert a HI if it's input is LO. Following from that is that you need the output to be passively pulled LO when both inputs are HI.

You might also look up information about RTL - Resistor-Transistor Logic. You can construct a single-transistor NAND gate with one PNP transistor and three resistors.

 

Thank you be80be. I can see now

 

Thank you WBahn for your reply. If I understand it correctly with typical NOT gates I would get a NOR gate.
And thank you for the suggestion about wired logic and RTL. Thats very interesting.

What kind of NOT gate are you talking about?

Let's consider a typical NOT gate, which actively asserts both output logic levels.

If you connect the outputs of two such NOT gates, what is the output if one input is HI and the other is LO?

Now, what if you use a single-ended output stage, meaning that it can only actively pull the outputThank in one direction and things have to be passively pulled in the other? This is called wired logic.

Consider that if either input is LO, you want the output to be HI, independent of what the other input is. That means that you need each NOT gate to actively assert a HI if it's input is LO. Following from that is that you need the output to be passively pulled LO when both inputs are HI.

You might also look up information about RTL - Resistor-Transistor Logic. You can construct a single-transistor NAND gate with one PNP transistor and three resistors.

 

If I understand it correctly with typical NOT gates I would get a NOR gate.

With only inverters, all you can get is NOT or buffers.

 

Thank you WBahn for your reply. If I understand it correctly with typical NOT gates I would get a NOR gate.

Nope.

Again. With typical NOT gates (meaning that the output is actively driven at all times) in which the outputs are tied together, what will the output be if the input of one NOT gate is HI and the input to the other is LO?

What will it be?

If you say that it will be HI, why will it be that?

If you say that it will be LO, why will it be that?