Constant Current Source driving a capacitor :LTSPICE Simulation Error

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hoyyoth

Joined Mar 21, 2020
217
I know that when a constant current source is driving a capacitor the output will be a ramp.

I tried to simulate the same in LTSPICE and got this error "ERROR: Node N001 is floating and connected to current source I1".

My circuit is given below.May I know where I went wrong.
1661528024521.png
 

crutschow

Joined Mar 14, 2008
30,791
Works for me.
Note that you need to use the UIC transient option to start from 0V.

What version of LTspice are you using?

1661532969292.png
 

Alec_t

Joined Sep 17, 2013
13,153
Still getting the same error
I don't see why.
"Across the cap" means the resistance is in parallel with the cap (not in series). You can use an external resistor (as Eric has shown), or you can right-click the cap symbol and edit the 'Equivalent Parallel Resistance' parameter of the cap itself.
 

Papabravo

Joined Feb 24, 2006
19,288
Despite the error in the Error Log, I believe LTspice is adding a conductance of "Gmin" across the inductor and running the simulation. The default value of Gmin on my system is 1E-12 which corresponds to 1TΩ. As you can see from the attached simulation the graph is a straight line long before the minimum conductance across the current source reaches 1E-12 by four orders of magnitude. A useful experiment would be to change the minimum Gmin value and see if it matches the above circuit without R1 present. The message in the Error Log should probably say WARNING, rather than ERROR, but LTspice is a simulator, rather than a compiler.
1661539190538.png
 
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Papabravo

Joined Feb 24, 2006
19,288
My off the wall hypothesis is that "uic" is short for "use initial conditions", as a synonym for "Skip initial operating point solution". This option also allows you to specify initial conditions in addition to skipping the process of solving for the initial condition.
 

WBahn

Joined Mar 31, 2012
27,395
I know that when a constant current source is driving a capacitor the output will be a ramp.

I tried to simulate the same in LTSPICE and got this error "ERROR: Node N001 is floating and connected to current source I1".

My circuit is given below.May I know where I went wrong.
View attachment 274754
The problem, most likely, is that each node should ideally have a DC path to ground so that the simulator can converge on the initial conditions.

Another way of putting this is that if a node could have multiple voltage values at startup, the simulator can't tell which one to use.

In this case the voltage on the output node at start-up depends on the initial charge stored on the cap, which is undefined. So the node voltage could be anything.

There are a number of ways to resolve the issue. One of the common ways is to do a DC startup analysis in which all node voltages are forced to zero and then any independent power sources are ramped from zero to their final values. I assume LTSpice supports this, but I don't know. This is often the first attempt when initial convergence is an issue, but it is a bit like using a sledgehammer and it's not guaranteed to work.

A better approach is to identify the troublesome nodes and explicitly give them initial conditions. In this case, LTSpice is telling you that node N001 is a troublesome node. So put an initial condition on it that makes sense, usually 0 V.

Not all simulation types use the initial condition commands, so there may still be simulations that are problematic.
 

Alec_t

Joined Sep 17, 2013
13,153
Interesting. I ran the post #1 sim with default Gmin of 1e-12, no internal or external resistor. I labelled the top of the cap as node C, added the directive .uic v(c)=0 and got this message in the error log :-
"WARNING: Node C is floating and connected to current source I1. It's .op solution is defined solely by a .ic statement."
So it doesn't look as though Gmin is being used to provide a default current path through the cap.
 
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Papabravo

Joined Feb 24, 2006
19,288
Interesting. I ran the post #1 sim with default Gmin of 1e-12, no internal or external resistor. I labelled the top of the cap as node C, added the directive .uic v(c)=0 and got this message in the error log :-
"WARNING: Node C is floating and connected to current source I1. It's .op solution is defined solely by a .ic statement."
So it doesn't look as though Gmin is being used to provide a default current path through the cap.
I performed my experiment of changing the default value of gmin and checking the box that says "Add GMIN across current sources", but the results did not correspond to my hypothesis. So I guess we need a better explanation.

1661611017800.png
 

eetech00

Joined Jun 8, 2013
3,418
I know that when a constant current source is driving a capacitor the output will be a ramp.

I tried to simulate the same in LTSPICE and got this error "ERROR: Node N001 is floating and connected to current source I1".

My circuit is given below.May I know where I went wrong.
View attachment 274754
If all you want to do is see the ramp, add the value IC=0 in the capacitor symbol. That specifies an initial condition for the voltage across the capacitor as "0" volts (so basically, the cap is initially a short circuit to ground).
You will then see a ramp, but it not very interesting as the the capacitor will continue charging and charging for the duration of the simulation.
 
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