Hi guys
We need to use a PIC24 we need a lot of IOs. Never use a PIC24 before, so I google and found this doc from Microchip:
PIC18F to PIC24F Migration: An Overview
There is an interesting graph on page 7 in the pdf, it says the PIC24F is "physically organized as 24 bits wide", but the PC address on the table only increase 2 every 3 bytes.
My question is:
If a PIC24F has 1000KB flash. Does it mean I can only actually use 750KB of the 1000KB, because the one instruction take up 1 phantom byte + 3 bytes (instruction).
or, if a PIC24F has 1000KB flash. I can actaully store 1500KB of data, because the address only increase 2 for every one instruction (3 bytes).

We need to use a PIC24 we need a lot of IOs. Never use a PIC24 before, so I google and found this doc from Microchip:
PIC18F to PIC24F Migration: An Overview
There is an interesting graph on page 7 in the pdf, it says the PIC24F is "physically organized as 24 bits wide", but the PC address on the table only increase 2 every 3 bytes.
My question is:
If a PIC24F has 1000KB flash. Does it mean I can only actually use 750KB of the 1000KB, because the one instruction take up 1 phantom byte + 3 bytes (instruction).
or, if a PIC24F has 1000KB flash. I can actaully store 1500KB of data, because the address only increase 2 for every one instruction (3 bytes).
