Problem:

Your company's internal studies show that a single core system is sufficient for the demand on your processing power; however, you are exploring whether you could save power by using two cores.

(a) Assume your application is 80% parallelizable. By how much could you decrease the frequency and get the same performance?

Applying the following formula:

\(Speedup_{overall} = (1 - Fraction_{enhanced} + \frac{Fraction_{enhanced}}{Speedup_{enhanced}})^{-1}\)

The fraction enhanced would be 0.8 since 80% can be parallelized.

The Speedup enhanced would be 2 since parallelizing on two cores would double the speed of that portion.

\(Speedup_{overall} = (1 - 0.8+ \frac{0.8}{2})^{-1}\)

So the overall speed up would be 5/3. Therefore the frequency can be multiplied by the reciprocal, 3/5 (or 0.6) to have the same performance as the single core processor. Does that make sense?

(b) Assume that voltage may be decreased linearly with the frequency. How much dynamic power would the dual core system require compared to the single core system?

Power is proportional to

\(C \times V^2 \times f\)

C is capacitive load, V is the operating voltage and f is the frequency. Since frequency is multiplied by 0.6, so is voltage, since it tracks linearly, giving a cubic reduction in power:

\(2 \times C \times (0.6 \times V)2 \times (0.6f) = 0.432 \times C \times V^2 \times f\)

I am multiplying by 2 at the beginning there since I figure there would be two cores using power. So this comes out to using less than

*half*the power of the original single core system. Now I am suspicious something is wrong.

(c) Now assume the voltage may not decrease below 25% of the original voltage. This is referred to as the voltage floor and any voltage lower than that will lose the state. What percentage of parallelization gives you a voltage at the voltage floor.

1/4 of the voltage would mean 1/4 of the frequency. If the frequency can by cut down to just 1/4 of the original frequency, then the speed up must have been by 4 times.

\(Speedup_{overall} = (1 - Fraction_{enhanced} + \frac{Fraction_{enhanced}}{Speedup_{enhanced}})^{-1}\)

\(Speedup_{overall} = 4 = (1 - x+ \frac{x}{2})^{-1}\)

\(0.25 = 1 - x+ \frac{x}{2} = 1 - \frac{x}{2}\)

This comes out to x = 1.5, where x is the fraction enhanced.

**That would mean 150% of the application would have to be parallelizable**! That just doesn't add up (pun intended, sorry)! Is there a mistake in my logic here? Was it just an arithmetic error?