Completed Project Shaped Tone-Burst Generator

This generator derives from the one designed by Siegfried Linkwitz. See his design and another design of a generator towards the bottom of the page that is linked to below.

https://www.linkwitzlab.com/sys_test.htm

The generator produces a tone to be amplified and reproduced by a loudspeaker system for the purpose of measuring frequency response of the loudspeaker. The frequency of the sine wave at input to the generator becomes the frequency response test frequency.

Reflected sound arriving to the measuring microphone and muddying accuracy of measuring the response is made easier to eliminate by limiting duration of the tone-burst to 5 cycles. Increasing and then decreasing amplitude of the tone-burst in steps reduces harmonic distortion of what for measurement purposes should be a pure tone.

The design of my generator directly adopts some of the circuit elements of his design. My design has the advantage that all of the components of it as this writing are widely available. There is much that is lacking here in terms of information as to how to about actually building my generator and I have done this in order to make it easier to explain how it functions. Nevertheless there is enough shown here to allow you to design a generator following my design.

The attached Figure 1 shows the circuit that when properly activated periodically produces the desired tone burst. Figure 2 shows the power supply connections to the circuits of both figures in a general way and the three circuit elements that produce the signals that are needed to make the circuit of Fig. 1 function as intended.

FIGURE 1, SEQUENTIAL SWITCHING CIRCUIT

On the left-hand side of Fig. 1 are four shift registers taken from two of the 4015 IC. The DATA terminal of the first shift register SR1 is connected to +6VDC of the power supply. The fourth output QD of SR1 is connected to the DATA input terminal of SR2. The outputs of SR2 are connected in order to a first input terminal of each of gates G1- G4. Output QD of SR2 is also connected to the DATA terminal of SR3.

The QA output of SR3 connects to a first input terminal of gate G5. Output QD of SR3 is intentionally unconnected. QC and QB of SR3 connect to the remaining open input terminals of respectively gates G5 and G4. QD of SR3 also connects to the DATA terminal of SR4. QA, QB, & QC of SR4 connect to the remaining open second input terminals of respectively gates G3 G2, and G1. QD of SR4 is intentionally unconnected (not used).

The output terminals of the five XOR gates connect sequentially to the control terminals of the analog switches going down the right-hand side of Fig. 1. The output of G1 connects to the control terminal of switch SW1, the output of G2 connects to the control terminal of SW2, etc.

The poles of switches SW2- SW5 of Fig. 1 connect to the throw of SW1. Each throw of the switches connect to the inverting input terminal of the op amp at the bottom right-hand side of Fig.1 through a fixed resistor. The resistance values of these resistors are those given in Linkwitz's generator. For my generator I substituted E12 resistance series values that were as close as possible to those given by Linkwitz.

FIGURE 2: CONTINUOUS SINE WAVE INPUT, RESET, AND CLOCK

Fig. 2A shows the power supply connections to the active components of the generator. Ground potential with respect to common equals -6V. The positive power supply terminal is +6V with respect to common.

At Fig. 2B is a 555 CMOS timer configured as an astable multivibrator. The period of the square wave output of the timer equals 1.5 seconds and its output resides low or at ground periodically for one-half second. The timer's output pin is connected to the reset terminal of the four shift registers of Fig. 1 by input K.

In cascade at Fig. 2C are a TL072B op amp configured as an inverting amp, a LM3393A comparator configured as a non-inverting zero crossing detector, and XOR gate G6 configured to produce a ground to +6V transition of short duration. The output terminal of G6 is connected to the clock terminals of of the shift registers of Fig. 1 by means of input L. Besides at input to the zero-crossing detector, the output of the inverting amp connects to the pole of switch S1 of Fig. 1 by input J.






SEQUENCE OF GENERATING A TONE BURST

The output pin of the timer of Fig. 2B residing at +6V (high) resets the shift registers of Fig. 1. This resetting causes all of the outputs of the registers to reside at ground or low. With the exception of the DATA terminal of SR1 connected to +6V, the three other DATA terminals are also sent low. The output of the timer residing at ground or low sets the shift registers or enables them to shift data.

The clock of Fig. 2C produces a positive voltage spike at output of the gate of the clock whenever the sine wave signal at input to the clock crosses zero volts or the common voltage. With the shift registers enabled, the voltage spike at input L of the registers of Fig. 1 results in clocking of all four registers.

The sine wave signal at input to the zero-crossing detector of Fig. 2C is also at input to the pole of switch SW1 of Fig. 1. Given the interconnectedness of the shift registers, gates and switches of Fig. 1, any change to the state of the switches and thus attenuation of the continuous sine wave at input J occurs when the voltage of the sine wave at input is to close to zero volts. This minimizes distortion of the tone burst as a result of the abrupt change of attenuation.

At Fig. 1, the first through fourth clocking of the enabled registers doesn't produce any change of the state of the switches. QD of SR1 is connected to the DATA terminal of SR2 and the other outputs of SR1 are unconnected. This is done to insure that clocking affecting the state of the switches doesn't occur while enabling of the registers is occurring. The fifth clocking results in output QA of SR2 sent high and given the logic of XOR gate G1 this in turn results in closing SW1.

The next four clocking of the registers of Fig. 1 causes QB, QC, and QD of SR2, and QA of SR3 to go from low to high. In turn this results in SW2- SW5 to close in sequence progressively reducing attenuation by the inverting amp at the bottom right-hand side of Fig. 1. With S1- S5 closed, the five resistors connected to the inverting input terminal of the TL072A amp are connected in parallel to the throw of SW1 producing the lowest input resistance to the amp and least attenuation of the continuous sine wave signal at input to the generator.

The extent of attenuation of the 6th half-wave of the tone burst is equal to that of the 5th half-wave by virtue of output QB of SR3 unconnected.That is, the tenth clocking of the registers produces no change of signal attenuation.

The eleventh clocking sends QC of SR3 of Fig. 1 high causing both input terminals of G5 to reside high, the output of gate G5 goes low, and switch SW5 is reopened. The 61k9 Ohm resistor is thus removed from being connected in parallel with the other four resistors and attenuation by the inverting amp is increased.

The twelfth and thirteen clocking continue the process of progressively increasing attenuation of each subsequent half-wave. The output terminals of gates G4, G3, and G2 in that order are sent low causing SW4, SW3, and SW2 to reopen and increasing attenuation of the continuous sine wave signal at input to the generator.

The fourteenth clocking sends output QC of SR4 of Fig. 1 high resulting in both of the two inputs of G1 to reside high. Thus the output terminal of G1 goes low opening SW1 and the tone burst output ceases. The circuit of Fig.1 is now in the state where all of the data and output terminals of the registers reside high (+6V). Additional clocking of the registers therefore doesn't alter switches S1- S5 in the open state. The shift registers must be reset before an additional tone burst can be generated. This is accomplished by the output of the square wave generator of Fig. 2B sent high and then returning to residing at ground every one and one-half seconds.

.................................