comparator circuit help

Thread Starter

unistudent

Joined Oct 27, 2019
5
How to make a full bit (2bit) comparator circuit using ONLY nand gates. I was able to do a 1bit comparator using only NAND gates, but how about for 2 bit, 4 bit? Wouldnt it be really large. I'm not sure if my class expects us to draw this out. we can't even use xor gates or inverters.

i have completed the kmaps and truth tables. I have to expressions Sum of products with just ands and Ors.
 

WBahn

Joined Mar 31, 2012
24,854
So take your best shot at doing it and show us what you get. Otherwise we have nothing to work with in order to help you.
 

Papabravo

Joined Feb 24, 2006
12,512
Two 2-bit quantities is 4 bits for inputs. You could have up to 3 outputs functions:
  1. A=B
  2. A<B
  3. A>B
Is that what your requirement is?
 

Thread Starter

unistudent

Joined Oct 27, 2019
5
So are you having trouble looking at a truth table, reading the SOP form and converting it to using the NAND function?
I already did the truth table and SOP form. I am comfortable in doing that type of stuff. I am having trouble drawing a logic circuit that implements a full comparator using only NAND gates. I was able to do it with just a half comparator, but at this larger scale, I don't how to start.

The full comparator inputs are x1, x0, y1, y0. Then three outputs. Less than, equal or greater than.
 

Papabravo

Joined Feb 24, 2006
12,512
OK. so if you could draw it out using AND gates and OR gates you would not have a problem. Is that correct?
If so, what you need to do is rewrite the SOP form using the NAND operator.

Side Note: are you familiar with the DeMorgan equivalents for the NAND gate?
We used to do this in words as follows:

NAND
A HIGH .AND. A HIGH is a LOW ; this is the way the gate is usually drawn
A LOW .OR. A LOW is a HIGH ; this is the same gate and it also implements the NAND function

Imagine that your comparator expression for EQUAL has 4 TERMS and each term is a LOW when it is true. So on the right hand side of your drawing you have a 4 input NAND gate that implements the .OR. function which would be:

a LOW .OR. a LOW .OR. a LOW .OR a LOW is a HIGH

Now each of those 4 terms is generated by a 4 input NAND gate, which uses either the input bit or it's complement to implement the following function

a HIGH .AND. a HIGH .AND. a HIGH .AND. a HIGH is a LOW

To get the complement of an input bit you connect that input bit to both inputs of a two input NAND gate and you are done.

You should be able to construct the drawing by inspection of the table.
 

Analog Ground

Joined Apr 24, 2019
169
The problems requires application of De Morgan's Theorems to change the boolean AND-OR function of the truth table to all NAND functions. The key is being able to apply De Morgans theorems,

/(A + B) = /A & /B
/(A & B) = /A + /B

to change the logic function so it is all NAND or /(A & B). Start simple and move on from there. It can be done because a NAND gate is logically complete. ALL logic functions can be converted to only NAND gates. NOR is also complete.
 

Papabravo

Joined Feb 24, 2006
12,512
I take it back. The question says two outputs only, and if both outputs are zero it indicates the inputs are equal
OK -- That makes sense. So now we only have two functions to make a truth table for. Did you understand Post#8 which shows the algebraic description of DeMorgan's theorem?
 

Thread Starter

unistudent

Joined Oct 27, 2019
5
OK. so if you could draw it out using AND gates and OR gates you would not have a problem. Is that correct?
If so, what you need to do is rewrite the SOP form using the NAND operator.

Side Note: are you familiar with the DeMorgan equivalents for the NAND gate?
We used to do this in words as follows:

NAND
A HIGH .AND. A HIGH is a LOW ; this is the way the gate is usually drawn
A LOW .OR. A LOW is a HIGH ; this is the same gate and it also implements the NAND function

Imagine that your comparator expression for EQUAL has 4 TERMS and each term is a LOW when it is true. So on the right hand side of your drawing you have a 4 input NAND gate that implements the .OR. function which would be:

a LOW .OR. a LOW .OR. a LOW .OR a LOW is a HIGH

Now each of those 4 terms is generated by a 4 input NAND gate, which uses either the input bit or it's complement to implement the following function

a HIGH .AND. a HIGH .AND. a HIGH .AND. a HIGH is a LOW

To get the complement of an input bit you connect that input bit to both inputs of a two input NAND gate and you are done.

You should be able to construct the drawing by inspection of the table.
Screenshot_29.png
something like this? I basically complemented by SOP twice. Is this a minimized gates amount?
 
Two things. The diagram is not clear and it should be redrawn to show all the corresponding minterms aligned vertically to allow easier interpretation. Second, determining if a function is minimized requires either showing equations, truth tables or K-maps, etc. Something in the way of a formal expression or proof. So, more should be shown. Also, since you are combining two functions (<, > to get =) ask yourself, are there any common minterms between the two?

By way of encouragement, I will say you are very close and show understanding of converting the functions to all NAND.
 
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