I am trying to design a CMOS toggle flip flop (TFF) for use in a low-bit count ripple counter (something like 4 to 6 bits). I do not need any ability to reset the flip flop (i.e., I can live with whatever state it powers up in). This circuit does not have to count fast, almost certainly less than 100kHz. My big constraint is transistor count.

Currently, the best I have come up with is a design that seems to work and requires 14 transistors. But this shaves only 4 transistors off of what I can get by taking a DFFR (D-type FF w/Reset) and stripping the reset support out of it.

My approach is basically a master-slave design using two latches, each made with a pair of cross-coupled inverters (so that takes 8 transistors) and then three transistors for each latch that are used to set or reset the latch, based on the state of the other latch, under the control of a write strobe (the master updates when the ws is LO and the slave updates with the ws is HI). My biggest concern with the design is the risk of both latches updating as the ws transitions, but I think that as long as I have the two transistors that the ws goes to right next to each other, the propagation delay through the latches will be sufficient to prevent it oscillating. Simulations seem to support that, at least so far.

What I would love to do is find some clever approach that doesn't use a master-slave arrangement but, instead, uses a few additional transistors on a single latch to give it edge-triggered behavior.

Anyone know how to design such a fundamental mode circuit, have a reference to a good text on it, or have any clever thoughts?

 

To me CMOS is a logic family, sounds like you wish to build toggle FFs from discrete parts. You mention CMOS then talk about transistors, maybe it is just me that is confused.

 

CMOS isn't a logic family, but rather a technology. Specifically, circuits designed using both NMOS and PMOS transistors. The "complementary" part of it does refer to implementing logic by using NMOS transistors to directly implement the LO side equations (POS terms) and then using the complement of that to implement the HI side equations using PMOS. But the term has long since become more generic than that, so a "CMOS process" is an IC fabrication process primarily intended to fabricate both NMOS and PMOS transistors and you have both analog and logic variants. The logic family just uses the name because it is a useful descriptor of what distinquishes that family from other families.

The circuit I am talking about is intended for fabrication as part of an ASIC and I am very tightly constrained on area available for this counter. So I am trying to design a FF at the transistor level that requires the fewest (and smallest) transistors possible.

 

If space is restriced, why not use a surface mount IC counter, 4040 etc? A toggle FF can be made fron 2 FET's.

 

If space is restriced, why not use a surface mount IC counter, 4040 etc?

Because when I say space is restricted, I'm talking about everything, not only the 4-bit counter but the tristate buffers and the analog circuitry driving the whole thing and the comparator interfacing the analog to the counter, having to fit in an area that is less than 64µm².

So imagine the cross section of a 29 AWG wire. I have to have a circuit that is small enough to fit 1000 of them in that area.

A toggle FF can be made fron 2 FET's.

How? I would love to see it. Unless you meant 2 FET's in conjunction iwth the 4040.