I'm trying to interface the TLV5616 with an mbed via SPI.

The connections I've made are as follows:

Note: mbed is powered from same 5V supply.

https://i.stack.imgur.com/duiLJ.png


I modified the mbed SPI helloworld prorgam:

#include "mbed.h"

SPI spi(p5, p6, p7); // mosi, miso, sclk
DigitalOut cs(p8);


int main() {

uint16_t fixed = 0x4000;
uint16_t value = 1000;

uint16_t final = value << 2;
final = fixed ^ value;
cs = 1;


spi.format(16,3);
spi.frequency(1000000);


// Select the device by seting chip select low
cs = 0;

// Send 0x8f, the command to read the WHOAMI register
spi.write(final);

// Deselect the device
cs = 1;


}

The first 4 bits (from the left) should be 0100, and the last 2 bit, 00. The 10-bit value goes in between. This is explained in the datasheet (http://www.tij.co.jp/jp/lit/ds/symlink/tlv5616.pdf).

I've used the bit pattern 0x4000, and XOR'd it with the 10-bit value, which is shifted by two. This should result in a bit pattern accepted by the DAC.

However, when measuring the DAC output, the value tends to stay around 200mv, sometimes going under, which leads me to believe something is not quite working. With a value of 1000, you would expect a value closer to 3.3v (REF).

I should mention that I haven't used a capacitor in this circuit, although I don't think it's necessary to test the basic functionality.

Any thoughts on what's going wrong?

 

How are you generating the FS frame sync signal?

 

How are you generating the FS frame sync signal?

I'm just pulling the pin low for the duration of the transmission.
Any idea which SPI mode I need? I wonder whether that has something to do with this...

CS (in the program) is connected to FS

 

I'm just pulling the pin low for the duration of the transmission.
Any idea which SPI mode I need? I wonder whether that has something to do with this...

CS (in the program) is connected to FS

I've not used this DAC before but there needs to be a separate FS (NOT CS) output from the controller that toggles low to high before SCLK and MOSI start. Sometimes the frame sync is embedded in the serial stream as a 'start bit' but here its a separate signal input on the DAC chip..

Looking at the data clock diagram it looks like SPI mode 1 I think.

MODE 1

 

I've not used this DAC before but there needs to be a separate FS (NOT CS) output from the controller that toggles low to high before SCLK and MOSI start. Sometimes the frame sync is embedded in the serial stream as a 'start bit' but here its a separate signal input on the DAC chip..

Looking at the data clock diagram it looks like SPI mode 1 I think.

MODE 1

The timing diagram seems to show FS just being brought low for the duration of the transmission. Are you saying I need to bring it low and then high again before data is sent? In which case, can I just do something like:

fs = 0;
wait(...);
fs = 1;

spi.write(...);

 

The timing diagram seems to show FS just being brought low for the duration of the transmission. Are you saying I need to bring it low and then high again before data is sent? In which case, can I just do something like:

fs = 0;
wait(...);
fs = 1;

spi.write(...);

I don't think it matters if it remains normally high or low after the FS low -> high toggle, it's the 'rising' that matters.

That edge resets the shift register to read bits until 16 bits are clocked in and then latched to the DAC analog output. Another FS 'rising' edge restarts that process.

 

I don't think it matters if it remains normally high or low after the FS low -> high toggle, it's the 'rising' that matters.

That edge resets the shift register to read bits until 16 bits are clocked in and then latched to the DAC analog output. Another FS 'rising' edge restarts that process.

In which case, what I have at the moment in code should be ok (although CS should be called FS), other than needing to change the mode to 1?
It seems my code is doing as you say; bringing the FS pin to low before the data is sent, and bringing it high, after.

 

In which case, what I have at the moment in code should be ok (although CS should be called FS), other than needing to change the mode to 1?
It seems my code is doing as you say; bringing the FS pin to low before the data is sent, and bringing it high, after.

The low to high FS pin toggle has to be completed before data is sent for each 16bit transfer sequence. If you wiring does that, it work unless there is a timing requirement with CS going low and FS toggle.

 

The low to high FS pin toggle has to be completed before data is sent for each 16bit transfer sequence.

Does it have to be low to high to low, as shown in the datasheet? And then I bring the pin high after the data has been sent?

 

Does it have to be low to high to low, as shown in the datasheet? And then I bring the pin high after the data has been sent?

Don't know if it's mandatory but I see it on just about every online wiring diagram for the chip. Pretty easy to test if the SPI mode is correct.

 

Don't know if it's mandatory but I see it on just about every online wiring diagram for the chip. Pretty easy to test if the SPI mode is correct.

I'll try all modes, and bring the pin, low-high-low before transmission, and high after. Does there need to be a delay between each transition of low to high, high to low? Or can I just do:

fs = 0;
fs = 1;
fs = 0;

spi.write();

 

I'll try all modes, and bring the pin, low-high-low before transmission, and high after. Does there need to be a delay between each transition of low to high, high to low? Or can I just do:

fs = 0;
fs = 1;
fs = 0;

spi.write();

MODE 1 should be the correct one.

From the datasheet:
twH(FS) Pulse duration, FS high MIN 20 ns
tsu(CS−FS) Setup time, CS low before FS↓ MIN 10 ns
tsu(FS−CK) Setup time, FS low before first negative SCLK edge MIN 8 ns
tsu(C16−FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS MIN 10 n

 

MODE 1 should be the correct one.

From the datasheet:
twH(FS) Pulse duration, FS high MIN 20 ns
tsu(CS−FS) Setup time, CS low before FS↓ MIN 10 ns
tsu(FS−CK) Setup time, FS low before first negative SCLK edge MIN 8 ns
tsu(C16−FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS MIN 10 n

Any chance you could modify my code above, just to make sure I'm doing this correctly?

 

Any chance you could modify my code above, just to make sure I'm doing this correctly?

No.

 

No.

Ok, I'll give it a go, and let you know how it works out. I'll post the code here. Cheers.

 

Ok, I'll give it a go, and let you know how it works out. I'll post the code here. Cheers.

No.

Unfortunately still no luck (I even tried with all modes).
This is the amended code:

#include "mbed.h"

SPI spi(p5, p6, p7); // mosi, miso, sclk
DigitalOut fs(p8);


int main() {
// Chip must be deselected
uint16_t fixed = 0x4000;
uint16_t value = 1024;

uint16_t final = value << 2;
final = fixed ^ value;
fs = 1;

// Setup the spi for 8 bit data, high steady state clock,
// second edge capture, with a 1MHz clock rate
spi.format(16,1);
spi.frequency(1000000);




fs = 0;
fs = 1;
wait(1);
fs = 0;

// Send 0x8f, the command to read the WHOAMI register
spi.write(final);

wait(1);

fs = 1;


}

 

How is CS being handled now?

 

How is CS being handled now?

CS is tied to GND, which is what the datasheet suggests (P.12).

 

How is CS being handled now?

At this point, do you suspect there may be something wrong with the chip? The wiring is exactly as shown in the schematic, and the code is what I posted in the previous comment. I just don't understand why this isn't working.

 

At this point, do you suspect there may be something wrong with the chip? The wiring is exactly as shown in the schematic, and the code is what I posted in the previous comment. I just don't understand why this isn't working.

It's time to use a o-scope and/or Channel Analyzer to verify the digital signals are at the right place with the right timing.