Floyd threw me a curveball on this one.
Question:
A load resistance is capacitively coupled to the emitter in Figure 77. In terms of signal operation, the load appears in parallel with RE and reduces the effective emitter resistance. How does this affect the voltage gain?
Circuit:
So @ Vout I add a 1uF cap and RL to ground. The cap has an ESR of 0.09Ω so it is negligible. The gain is 0.998. RL is parallel so the only effect I see @ Vout is the coupling capacitor ESR? "load appears in parallel with RE and reduces the effective emitter resistance" Av= RE/er + RE So does that become Av = RE||RL/ re + RE||RL ? Apparently not (and I wouldn't think so) since the answer is given as 1% without even knowing what the value of RL is. Due to the coupling cap, the load resistance may be in parallel but has no effect on the transistor biasing is how I see it. The DC bias is all I am given here. I have no signal.
Sam
Question:
A load resistance is capacitively coupled to the emitter in Figure 77. In terms of signal operation, the load appears in parallel with RE and reduces the effective emitter resistance. How does this affect the voltage gain?
Circuit:
So @ Vout I add a 1uF cap and RL to ground. The cap has an ESR of 0.09Ω so it is negligible. The gain is 0.998. RL is parallel so the only effect I see @ Vout is the coupling capacitor ESR? "load appears in parallel with RE and reduces the effective emitter resistance" Av= RE/er + RE So does that become Av = RE||RL/ re + RE||RL ? Apparently not (and I wouldn't think so) since the answer is given as 1% without even knowing what the value of RL is. Due to the coupling cap, the load resistance may be in parallel but has no effect on the transistor biasing is how I see it. The DC bias is all I am given here. I have no signal.
Sam