Hello, while reading from Razavi notes on bandgap reference design, it states that 2 pnp connected in series (collect of top pnp is connected with the emitter of the bottom transistor) are not fesiable in CMOS technology because the collector of the collectors at the top are not grounded. Why do we have to ground the collector of a transistor? Will will it apply as when if the configuration in made by npn transistors? If you happened to have Razavi Design of Analog CMOS please refer to pg 388. Thanks

 

Originally posted by surreyian@Jan 16 2005, 10:04 PM
Hello, while reading from Razavi notes on bandgap reference design, it states that 2 pnp connected in series (collect of top pnp is connected with the emitter of the bottom transistor) are not fesiable in CMOS technology because the collector of the collectors at the top are not grounded. Why do we have to ground the collector of a transistor? Will will it apply as when if the configuration in made by npn transistors? If you happened to have Razavi Design of Analog CMOS please refer to pg 388. Thanks

[post=4610]Quoted post[/post]​

hi,

let me give you something to think about, you have to know how electron flows in a PNP and how current flows thru it. only then that you would realize what the author meant. likewise check on the CMOS topology (basic principle)