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code VHDL pour FIFO asynchrone

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Safa1

Joined Mar 15, 2012
1
Bonjour

Je veux écrire un code VHDL pour réaliser un FIFO asynchrone .
L'entité est la suivante :

ENTITY fifo_async is
PORT (
data_i : IN STD_LOGIC;
wr_en_i : IN STD_LOGIC; --write enable
rd_en_i : IN STD_LOGIC; --read enable
tck_ret_i : IN STD_LOGIC; -- reading clock
clk_i : IN STD_LOGIC; -- writing clock
reset_async_i : IN STD_LOGIC; --reset
data_o : OUT STD_LOGIC:='0';
full_o : OUT STD_LOGIC:='0';
empty_o : OUT STD_LOGIC:='0'
);
END tdi_fifo_async;


Merci pour votre aide.
 
Brownout

Brownout

Joined Jan 10, 2012
2,390
I think he wants help making an asychronous FIFO.

Creating an asychronous FIFO is exceedingly difficult. I started one once, but never finished. I recommend looking at Open Cores. I didn't find one when I checked there, but that was about a year ago.
 
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