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Hi what is the problem of using low pass filter before OR gate, i hear that CMOS not like input capacitor but i do not know why?

 

The reason why has to do with the transition time of the input signal. The longer the rise time or fall time of the signal the more time the gate is in the linear region effectively shorting the power supply to ground at the output.

 

Thanks so much , can you please explain more(how the power supply get shorted at the output)

 

Thanks so much , can you please explain more(how the power supply get shorted at the output)

Slowly transition edges (signals) increase the time that both output transistors are on.

 

Slowly transition edges (signals) increase the time that both output transistors are on.

Thanks, do you mean increasing the linear region, because it can be on some time and off some times, so the problem in the linear region where the switch has voltage and current so the dissipation is high and it can blow the device.
is what i understand is right ?

 

Thanks, do you mean increasing the linear region, because it can be on some time and off some times, so the problem in the linear region where the switch has voltage and current so the dissipation is high and it can blow the device.
is what i understand is right ?

That's the basic idea. There's a maximum power dissipation figure for all devices in a package. So it's okay to operate in the linear region as long as you keep power dissipation under the allowed limit.

Inverting gates can be biased in the linear region and be used as amplifiers.

 

Another problem with a slow rise/fall time at the gate input is that it can oscillate in the linear region due to stray capacitive feedback.
You can use a low-pass filter at the input if you use a Schmitt-trigger device such as the CD4093, CD4106, CD4583, CD4584, or CD4106, as they will give a sharp transition at the output no matter how slowly the input changes.
There should be equivalents in the 74HC series.
Here's a list of 74x devices. Look for those with a Schmitt-trigger input.

 

Another problem with a slow rise/fall time at the gate input is that it can oscillate in the linear region due to stray capacitive feedback.
You can use a low-pass filter at the input if you use a Schmitt-trigger device such as the CD4093, CD4106, CD4583, CD4584, or CD4106, as they will give a sharp transition at the output no matter how slowly the input changes.
There should be equivalents in the 74HC series.
Here's a list of 74x devices. Look for those with a Schmitt-trigger input.

Thanks so much, do you the maximum input capacitance i can use it with this part
https://media.digikey.com/pdf/Data Sheets/ST Microelectronics PDFS/M74HC4075.pdf

 

That's the basic idea. There's a maximum power dissipation figure for all devices in a package. So it's okay to operate in the linear region as long as you keep power dissipation under the allowed limit.

Inverting gates can be biased in the linear region and be used as amplifiers.

Thanks so much , can you help me to figure the maximum capacitance i can use it for this part
https://media.digikey.com/pdf/Data Sheets/ST Microelectronics PDFS/M74HC4075.pdf

 

Thanks so much , can you please explain more(how the power supply get shorted at the output)

Sure. The totem-pole output has a p-channel FET and an n-channel FET. The output is where the two FETS are connected together. When the input is in the transition region about Vdd/2 both FETS are in the on-state and a substantial current begins to flow. The longer the transition lasts, the more time the "short" has to generate heat. Enough heat will kill a part. That is also why CMOS inputs must never be left floating.

 

Thanks so much , can you help me to figure the maximum capacitance i can use it for this part

You don't want use a capacitor with that part.
You need to use one with a Schmitt-trigger input.
That's why the build those parts.
Otherwise you may get unsatisfactory/erratic behavior of the circuit.

 

Another problem with a slow rise/fall time at the gate input is that it can oscillate in the linear region due to stray capacitive feedback.
You can use a low-pass filter at the input if you use a Schmitt-trigger device such as the CD4093, CD4106, CD4583, CD4584, or CD4106, as they will give a sharp transition at the output no matter how slowly the input changes.
There should be equivalents in the 74HC series.
Here's a list of 74x devices. Look for those with a Schmitt-trigger input.

Hi , i can not find SMT 3inputs or gate with a Schmitt-trigger input., do you know one?

 

Hi , i can not find SMT 3inputs or gate with a Schmitt-trigger input., do you know one?

Use a single Schmidt Trigger buffer in front of the 3-input gate

https://www.tme.eu/en/details/nc7sp...MIlKzLybex3gIVB-DICh2caAssEAQYAyABEgIFD_D_BwE
http://www.ti.com/product/SN74LVC1G17

 

Hi , i can not find SMT 3inputs or gate with a Schmitt-trigger input., do you know one?

No.
But you could use two Schmitt-trigger 2-input OR gates in tandem (SN74HC7032) to give a 3-input OR function.

 

No.
But you could use two Schmitt-trigger 2-input OR gates in tandem (SN74HC7032) to give a 3-input OR function.

Thanks so much

 

Use a single Schmidt Trigger buffer in front of the 3-input gate

https://www.tme.eu/en/details/nc7sp...MIlKzLybex3gIVB-DICh2caAssEAQYAyABEgIFD_D_BwE
http://www.ti.com/product/SN74LVC1G17

I think i will use 3 one for each input.

 

EDIT - these parts aren't suitable - they tolerate transitions slower than "normal" but aren't really appropriate for the application - the maximum rise and fall times are spec'd in nanoseconds per volt The description of them as having Schmitt trrigger inputs is rather deceptive (NXP datasheet; TI sheet makes no such mention).

74LVC1G332 - three input OR with Schmitt trigger, or if you rework the input circuit to be active low instead of active high, you can do task with a single 74LVC1G10 (applying DeMorgan's theorem).

 

Here is a good ap note on CMOS risetime issues -

http://www.ti.com/lit/an/scba004d/scba004d.pdf


Regards, Dana.

 

Here is a slow rise time time sim with noise and results out of the
gate -



Regards, Dana.

 

EDIT - these parts aren't suitable - they tolerate transitions slower than "normal" but aren't really appropriate for the application - the maximum rise and fall times are spec'd in nanoseconds per volt The description of them as having Schmitt trrigger inputs is rather deceptive (NXP datasheet; TI sheet makes no such mention).

74LVC1G332 - three input OR with Schmitt trigger, or if you rework the input circuit to be active low instead of active high, you can do task with a single 74LVC1G10 (applying DeMorgan's theorem).

The original question wasn't about looking for an optimal part, but any collection candidate parts for further consideration. This exercise illustrates the real point of the thread, which is that a TS must evaluate all suggestions with respect to his original requirements which may or may not be explicitly revealed in the thread. In addition a good designer will read and thoroughly understand a datasheet when considering any part for use in in a product or a project.