Hi All,
Background: I have a 2 layer board with Atmega164 (SMD) running from an external 8MHz crystal. There's a ground island underneath the micro with local 100nF decoupling caps, a bulk 3900uF cap, and two series regulators, and the crystal circuit pretty much follows the ATMEL layout notes without the ground island on the top layer too. The crystal is placed < .5" from the uC, as tight as I could get it with the load caps and the nearest decoupling cap, with the crystal on it's own in the corner. I've read like 3 books on EMC and like hundreds of app notes, so I felt like I knew what I was doing but everywhere I can measure, I see about 2mV of clock harmonics (30-100MHz range) on both the power and ground traces/islands, even traces a foot away. The interference's polarity changes if I inspect ground vs. power, so it appears conducted.
I've tried throwing SMD ferrite beads (1k @ 100MHz...the widest bandwidth devices I could find) at the problem to see if I can track it down, but I've only managed to reduce the noise by a little. I've tried configuring the uC osc, and surprisingly fullswing appears to give the lowest noise, even over the internal clock. I've also added a few more ceramic caps in places, no change. I notice a slight change in frequency or something when I touch the crystal's case, but every other place I've touched doesn't affect things.
Questions: Is there a way to track this down using the basic scope/signal gen/DMM toolkit? At 8MHz+, I'd think return current would flow directly under the traces back to the source, so how is it going everywhere? Given that it appears differential, from power to ground (and every trace connected to the supply) I assume that means it doesn't have an easy enough path back to ground from a capacitive coupling path (I assume to power), could this be correct? Any clues I'm missing?
I'm sure there's questions I don't even know to ask and details I've left out but thank you for reading/helping! I'm at my wits end!
Background: I have a 2 layer board with Atmega164 (SMD) running from an external 8MHz crystal. There's a ground island underneath the micro with local 100nF decoupling caps, a bulk 3900uF cap, and two series regulators, and the crystal circuit pretty much follows the ATMEL layout notes without the ground island on the top layer too. The crystal is placed < .5" from the uC, as tight as I could get it with the load caps and the nearest decoupling cap, with the crystal on it's own in the corner. I've read like 3 books on EMC and like hundreds of app notes, so I felt like I knew what I was doing but everywhere I can measure, I see about 2mV of clock harmonics (30-100MHz range) on both the power and ground traces/islands, even traces a foot away. The interference's polarity changes if I inspect ground vs. power, so it appears conducted.
I've tried throwing SMD ferrite beads (1k @ 100MHz...the widest bandwidth devices I could find) at the problem to see if I can track it down, but I've only managed to reduce the noise by a little. I've tried configuring the uC osc, and surprisingly fullswing appears to give the lowest noise, even over the internal clock. I've also added a few more ceramic caps in places, no change. I notice a slight change in frequency or something when I touch the crystal's case, but every other place I've touched doesn't affect things.
Questions: Is there a way to track this down using the basic scope/signal gen/DMM toolkit? At 8MHz+, I'd think return current would flow directly under the traces back to the source, so how is it going everywhere? Given that it appears differential, from power to ground (and every trace connected to the supply) I assume that means it doesn't have an easy enough path back to ground from a capacitive coupling path (I assume to power), could this be correct? Any clues I'm missing?
I'm sure there's questions I don't even know to ask and details I've left out but thank you for reading/helping! I'm at my wits end!