Hi,

We are working on a class AB amplifier circuit to drive acoustic sensors. Our schematic is shown below.

Analog_In is 2.5Vpp 140kHz Sinewave, and we have to get 250Vrms at the output of the transformer. 50k Resistor and 231pF Capacitor simulates the load model of sensor at 140kHz. R5 is for current sensing.

Everything was fine until connecting 231pF load capacitance. After that our darlington pairs U3 and/orU4 are blowing up with resistors R6 and/or R7. Blowing up scenario usually occurs at first power up, or when there is not any analog_input (floating or output of at signal generator at High Z), or sometimes power off and then power on again.

Do you have any idea to make this circuit operational? Thanks in advance.

 

It may be oscillating with the capacitive load.

That looks like an LTspice schematic. If so post the .asc file.
What were the simulation results?
Have you looked at the phase-margin?

 

Hi crutschow,

Thank you for your comment.

You can find asc file and component library as attachment.

I have not looked at phase-margin. Actually I am new at this topic, I can plot phase-margin at LTSpice but I could not know yet how can I evaluate this plot. I will work on learning about phase-margin. At that time if you have any suggestion, it will be appriciated.

 

Have you looked at the phase-margin?

I have looked at now, and as I understand phase margin is OK to be 135 degrees? Please find it as attachment.

 

I have looked at now, and as I understand phase margin is OK to be 135 degrees? Please find it as attachment.

You need to look at the phase at the frequency where the gain goes to 0dB.

 

As I see there is no 0dB attenuation?

 

Do the AC analysis with 1V AC input and look at the output.
My simulation shows a large peak in the gain at about 15kHz (below), which is a likely frequency of oscillation.

 

Do the AC analysis with 1V AC input and look at the output.
My simulation shows a large peak in the gain at about 15kHz (below), which is a likely frequency of oscillation.

OK I have seen this frequency of oscillation, but I am working at 140kHz. I could not understand the relation between them

 

OK I have seen this frequency of oscillation, but I am working at 140kHz. I could not understand the relation between them

That's because there is no relation between them.
The oscillation occurs at the frequency where positive feedback occurs in the feedback loop due to loop phase-shift.
It has nothing to do with the signal frequency.
So you need to add a compensation network in the loop to prevent that phase-shift, which is not always a trivial solution.

 

It may be oscillating with the capacitive load.

That looks like an LTspice schematic. If so post the .asc file.
What were the simulation results?
Have you looked at the phase-margin?

That would be my first suspicion too. This is why I LOVE my digital sampling scope. It picks up these fleeting glitches.

 

See

 

That's because there is no relation between them.
The oscillation occurs at the frequency where positive feedback occurs in the feedback loop due to loop phase-shift.
It has nothing to do with the signal frequency.
So you need to add a compensation network in the loop to prevent that phase-shift, which is not always a trivial solution.

Thank you for your comment. Bordodynov suggested a compensation network, we will try this. Please see comments below message.

 

See
View attachment 122921 View attachment 122922

Hi Bordodynov,

Thank you for your valuable effort and suggestion. Sorry for the late answer since we were working on different project.

There is a decrease in gain but more stable. It is possible but hard to implement this compensation to our manufactured pcb, therefore it is waiting as second plan. Our first plan is removing C12 (10uF) and replacing C11 with 220nF. When we tested we have seen a reduced gain but more stable network. Now we are manufacturing new transformers with 42 and 45 ratios to test first plan and second plan.

Do you have any comment about our first plan?

Best regards.

 

Hi Bordodynov,

Thank you for your valuable effort and suggestion. Sorry for the late answer since we were working on different project.

There is a decrease in gain but more stable. It is possible but hard to implement this compensation to our manufactured pcb, therefore it is waiting as second plan. Our first plan is removing C12 (10uF) and replacing C11 with 220nF. When we tested we have seen a reduced gain but more stable network. Now we are manufacturing new transformers with 42 and 45 ratios to test first plan and second plan.

Do you have any comment about our first plan?

Best regards.

Hi Bordodynov,

In addition to my previous message I have realized that your Darlington pair spice codes and ours are very different. We have found these .libs from onsemi website. With our library in simulation something is missing that we could not know, your library seems more realistic but extreme results. For example, in our simulation Vbe voltages of TIP121 and TIP127 are are max 1.5V, but in yours it is 12V. We have also suspcious for exceeding Vbe voltage treshold (5V). Could you please check your spice models? Our spice models is attached to message.

Thank you.

 

Hi,

At our test I think we may found a clue. with 330nF test output signal was distorted by time and then darlingtons were blowed up. You can find signal at the attched video.

I think it is related with opamp temperature and when opamp goes thermal shutdown output of opamp floats then the rest of the circuit blows up. It will be high current or floating Vbe voltages, I could not know yet. Do you have any idea or comment?

 

Hi Bordodynov,

In addition to my previous message I have realized that your Darlington pair spice codes and ours are very different. We have found these .libs from onsemi website. With our library in simulation something is missing that we could not know, your library seems more realistic but extreme results. For example, in our simulation Vbe voltages of TIP121 and TIP127 are are max 1.5V, but in yours it is 12V. We have also suspcious for exceeding Vbe voltage treshold (5V). Could you please check your spice models? Our spice models is attached to message.

Thank you.

I have very greater collection of the models. I shall even say more. At the beginning initially I used such models as you have sent. But studied datasheet I have changed these models on that which you have found in my file. Attentively see on nominal value of the resistor R2
My model:
.SUBCKT TIP121 1 2 3
* TERMINALS: C B E
* 80 Volt 5 Amp NPN Darlington Transistor
Q1 1 2 4 QPWR .1
Q2 1 4 3 QPWR
R1 2 4 10K
R2 4 3 150
........
Your model:
Q1 1 2 4 qmodel
Q2 1 4 3 q1model 2.80758
D1 3 1 dmodel
R1 2 4 10000
R2 4 3 1000
....
and

 

See how I shape piezo and transformer:

 

We have solved the problem. We put 100p Capacitor parallel to negative feedback resistor, then increse feedback resistor to 20kOhm and Transformer ratio to 45.

Thank you for your support.