I was thinking about a type of protection circuit for the gated SR flip-flop above. There might be a situation where you want to disable excessive flip-flopping by pulling the enable low if Q transitions more than say 5 times within a time period of say 1 second.

After that protection feature "trips", an external reset would be required to allow normal operation again.

I have some thoughts about how to implement this, but probably there are better ideas in the hive, requiring fewer components.

My thinking was to have a counter that counts (rising) edges of Q, and that counter gets automatically reset (every 1 second), except if the counter hits a target value.

 

My thinking was to have a counter that counts (rising) edges of Q, and that counter gets automatically reset (every 1 second), except if the counter hits a target value.

That would work for that particular 1 second interval, but what about the interval that starts at 0.5 second after you start the count and goes to 1.5 second. You could have more that 5 counts in that interval and it wouldn't be detected.
Is that a concern in your application?

If so, you could use an up-down counter type circuit where you use a clock to generate 5 pulses per second to count down.
You would count the signal input pulses up.
The counter would need to stop counting down when it reaches zero.
So if the counter stays above zero for more than 1 second, you would freeze the flip-flop.

You could use an up/down counter such as a 74193.
You would need to shorten the pulses to the minimum necessary to clock the counter to minimize the problem of both clocks being high at the same time, which the counter can't handle.

 

That is a good point you raise regarding the interval.

"If the counter stays above zero for more than 1 second, you freeze" - how to implement that?

 

..............
"If the counter stays above zero for more than 1 second, you freeze" - how to implement that?

One way is to have the first counter zero-count reset a second counter clocked by a 5Hz signal, with count 5 of the second counter being the freeze signal.
So if the second counter is not reset with a first counter zero-count by the time it gets to count 5, you have a freeze.