I have designed a single stage CE voltage amplifier. The emitter resistor is totally
bypassed due to the high voltage gain requirement of 80. According to my
calculations, the maximum ac output voltage should be 2.95 peak. All of this is
based on my Heathkit Transistor design course guidelines for CE design.

Using LTSpice, there is no way that I can obtain an output of that magnitude when
I run a simulation.

Also, when I design a CE with an emitter bypass capacitor (either full or
partial bypass) the calculated value using, CE = 3.18 / (f1 * RE) always
results in a value that causes a lot of distortion. If a calculated value ends up
being 16uF, I end up having to use perhaps 500uF.

Thoughts?

David

 

hi 55,
Could you post calculations.
E

 

The capacitor impedance should be low compared to the transistor emitter internal resistance, not the acrual emitter resistance.
https://forum.allaboutcircuits.com/...-capacitor-value-in-art-of-electronics.41362/

 

Calculations:

rL = RC * RL / RC + RL = 2.03K * 10K / 2.03K + 10K = 1.69K

vo_plus = ICQ * rL = 1.75mA * 1.69K = 2.96 Volts

vo_minus = VCEQ = Vc - Ve = 6.49V - 3.47V = 3.02 Volts

vo_Max = Lesser of vo_plus and vo_minus = 2.96 Volts

 

The capacitor impedance should be low compared to the transistor emitter internal resistance, not the acrual emitter resistance.
https://forum.allaboutcircuits.com/...-capacitor-value-in-art-of-electronics.41362/

Using Xc = 0.1 * re' = 0.1 * 20.76 ohms = 2.1 ohms

Ce = 1 / 2 * Pi * f1 * Xc = 1 / (6.28) * (100Hz) * (2.1 ohms) = 758uF

 

hi,
Consider you have 2mVppk input signal and you want say 3Vppk out, I make the required gain 3v/2mV = 1500.
What is the Beta of a 2N3904.?
E

 

hi,
Consider you have 2mVppk input signal and you want say 3Vppk out, I make the required gain 3v/2mV = 1500.
What is the Beta of a 2N3904.?
E

The minimum Beta should be 100 on average. Therefore my gain is constrained to
be no greater than 100.

If I take 2.95 V pk / 95 = 31 mV pk. If I feed a 31 mV pk signal in it clips big time.

 

hi,
It does give 2.8Vppk out at the Collector, with distortion.

If you recall we posted about the linear region/range on another Thread.
E

 

You must understand that is it impossible to get such a high voltage gain and low distortion at the same time in such a simple amplifier.

 

Using LTSpice, there is no way that I can obtain an output of that magnitude when

A tip. Try to increase the output capacitor to 500uF and look then once again.

Also, in simulation you have use RL = 5.6kΩ not 10kΩ

And for RL= 5.6kΩ you will never get more than:
Vo_+max = (Vcc - Vc) * RL/(Rc + RL) ≈ (10V - 6.5V) * 5.6k/(2k + 5.6k) ≈ 2.5V when BJT is completely cut-off

Also, when I design a CE with an emitter bypass capacitor (either full or
partial bypass) the calculated value using, CE = 3.18 / (f1 * RE) always
results in a value that causes a lot of distortion. If a calculated value ends up
being 16uF, I end up having to use perhaps 500uF.

This is normal because you must understand that with CE capacitor the transistor voltage gain will depend on actual collector current due to the fact the transistor transconductance (gm ≈ 1/re) will vary with the current collector.

If we asume the quiescent current equal to Icq = 1.7mA the gain will be equal around :

re = 26mV/1.7mA = 15.2Ω

Rc||RL = 2kΩ||10kΩ ≈ 1.67kΩ

Av = 1.67kΩ/15.2Ω ≈ 109V/V


But during the positive cycle at the collector (when collector voltages approach Vcc), transistor collector current will drop (decreases) let us say to 170μA.

At this point the voltage gain will be equal to Av ≈ 1.67kΩ/153Ω ≈ 11V/V

On the other end (during the negative cycle ) the collector current increases let us say to 3.6mA (re ≈ 7.2Ω) and the gain is Av ≈ 1.67kΩ/7.2Ω ≈ 230V/V.

This means the gain will very from 11V/V to 230V/V

So during the whole cycle, you will see the large variation in the voltage gain, with the lowest voltage gain at the point when the collector voltage reaches the highest value and the highest voltage gain when the voltage at collector reaches the lowest value.
And due to this effect (wide voltage gain variation in the rhythm of the input signal), you see that the upper part of a curve is flattened (strongly rounded) and the lower part of a curve look sharper and more pointed.
Because your amplifier voltage gain is constantly changing in the rhythm of the input signal.

And to prevent this from happening you need to apply a negative feedback into your circuit.

 

A tip. Try to increase the output capacitor to 500uF and look then once again.

Also, in simulation you have use RL = 5.6kΩ not 10kΩ

And for RL= 5.6kΩ you will never get more than:
Vo_+max = (Vcc - Vc) * RL/(Rc + RL) ≈ (10V - 6.5V) * 5.6k/(2k + 5.6k) ≈ 2.5V when BJT is completely cut-off






This is normal because you must understand that with CE capacitor the transistor voltage gain will depend on actual collector current due to the fact the transistor transconductance (gm ≈ 1/re) will vary with the current collector.

If we asume the quiescent current equal to Icq = 1.7mA the gain will be equal around :

re = 26mV/1.7mA = 15.2Ω

Rc||RL = 2kΩ||10kΩ ≈ 1.67kΩ

Av = 1.67kΩ/15.2Ω ≈ 109V/V


But during the positive cycle at the collector (when collector voltages approach Vcc), transistor collector current will drop (decreases) let us say to 170μA.

At this point the voltage gain will be equal to Av ≈ 1.67kΩ/153Ω ≈ 11V/V

On the other end (during the negative cycle ) the collector current increases let us say to 3.6mA (re ≈ 7.2Ω) and the gain is Av ≈ 1.67kΩ/7.2Ω ≈ 230V/V.

This means the gain will very from 11V/V to 230V/V

So during the whole cycle, you will see the large variation in the voltage gain, with the lowest voltage gain at the point when the collector voltage reaches the highest value and the highest voltage gain when the voltage at collector reaches the lowest value.
And due to this effect (wide voltage gain variation in the rhythm of the input signal), you see that the upper part of a curve is flattened (strongly rounded) and the lower part of a curve look sharper and more pointed.
Because your amplifier voltage gain is constantly changing in the rhythm of the input signal.

And to prevent this from happening you need to apply a negative feedback into your circuit.

On Saturday, you sent me an LTSpice file with a 9.1 ohm resistor in series with C3.
Is this the negative feedback that you were speaking of? How did you arrive at the
values for C3 and the 9.1 ohm resistor?

Thanks,

David

 

Does everyone notice that the AC voltage gain has nothing to do with beta? Beta is current gain, not voltage gain.

A transistor without negative feedback has severe distortion (the top of the waveform appears to be squashed) as its output waveform approaches cutoff because its voltage gain is reduced near cutoff.

Here is a common-emitter NPN transistor without any negative feedback: (Its distortion is severe.
Here is a transistor showing its voltage gain when it is biased so that its collector current is high and is low:

 

Does everyone notice that the AC voltage gain has nothing to do with beta? Beta is current gain, not voltage gain.

A transistor without negative feedback has severe distortion (the top of the waveform appears to be squashed) as its output waveform approaches cutoff because its voltage gain is reduced near cutoff.

Here is a common-emitter NPN transistor without any negative feedback: (Its distortion is severe.
Here is a transistor showing its voltage gain when it is biased so that its collector current is high and is low:

Where is the emitter resistor? Where is the negative feedback?

 

Where is the emitter resistor? Where is the negative feedback?

The waveforms are extremely distorted because there is no negative feedback. An emitter resistor without a bypass capacitor or a resistor from the collector to base and a series input resistor apply negative feedback.
Of course negative feedback reduces the voltage gain.