Hmm. We are using the same .asc file. Have I specified some incorrect parameters in the Spice directives maybe.hi,
My LTS result is close to Jony's
E
Hmm. We are using the same .asc file. Have I specified some incorrect parameters in the Spice directives maybe.hi,
My LTS result is close to Jony's
E
Why didn't you use the LTspice file that I upload in my previous answer? Where I properly set-up the transient analysisThe THD is then 0.65% in LTSpice.
I have done that now and I get the 0.2%. I guess I don't know how to use the Transient thing properly.Why didn't you use the LTspice file that I upload in my previous answer? Where I properly set-up the transient analysis
How you define and measure this offset?There is still an offset voltage of ≈ -7mV. If I increase the capacitor value to 1500 uF
then the offset falls to ≈ -2.7mV.
Show me the example.This is why I was saying that the CNF formula doesn't
seem to yield a good value.
What I mean is that the vout waveform starts at a voltage less than zero. Like -7 mV or -2.7 mV. It is evident in the transient graph. Perhaps the term "offset" was incorrect.How you define and measure this offset?
Show me the example.
I understood that the base line should always be zero volts. If the CNF formula yielded a larger capacitor value, thisSo, this "offset" is a big problem for you? Why?
Why ?I still have a problem determining the required value of an emitter bypass
capacitor mathematically
Why 100μF wotks nicely and 8.85μF don't work for you ?Using LTS, a value of
100uF works nicely but my calculated values are always much smaller,
like 8.85uF.
My point is this. Anyone can plug values in an LTS sim and getWhy ?
Why 100μF wotks nicely and 8.85μF don't work for you ?
Where did you try to find this answer? You need some basic circuit theory book for sure.So far with all my research,
I have not been able to find the answer.
Hi:I cannot understand why you are so bothered about the very small "pseudo offset" in the first place? Which is not a real offset (DC voltage at the output), but a phase shift caused by a capacitor in a circuit. It's physically impossible to have an "offset voltage" (DC voltage) after the signal passes the capacitor in steady-state.
Also, when you are using this equation C = 1/(2 * pi * Fc *R) to compute the capacitor value you should keep in mind that at this frequency (Fc) the phase shift is equal to 45° degrees.
Where did you try to find this answer? You need some basic circuit theory book for sure.
Yes, the offset is distortion. It is normal for a single common-emitter NPN transistor to squash the positive going peak compared to the normal or extended negative-going peak. The voltage gain of the transistor is reduced when it nears cutoff. It causes even harmonics distortion.I understood that the base line should always be zero volts. If the CNF formula yielded a larger capacitor value, this offset would be much smaller. Is this offset not a form of distortion?
In your amplifier there are three capacitors, which are high-pass filters. If you want to equalize the time constants, thenHi:
I still have a problem determining the required value of an emitter bypass
capacitor mathematically. See attached schematic. Using LTS, a value of
100uF works nicely but my calculated values are always much smaller,
like 8.85uF.
View attachment 159575
Any help would be appreciated.
David
There is another harmful effect due to the presence of a capacitor in the emitter of the transistor. This is the detection effect. This effect leads to a dynamic change in the operating point of the transistor.
by Jake Hertz
by Jerry Twomey
by Jake Hertz
by Jake Hertz