CE - Full Emitter Resistor Bypass - Computing Capacitor Values

Thread Starter

elec_eng_55

Joined May 13, 2018
214
Why didn't you use the LTspice file that I upload in my previous answer? Where I properly set-up the transient analysis
I have done that now and I get the 0.2%. I guess I don't know how to use the Transient thing properly.
I don't understand why the different settings give a different answer.

There is still an offset voltage of ≈ -7mV. If I increase the capacitor value to 1500 uF
then the offset falls to ≈ -2.7mV. This is why I was saying that the CNF formula doesn't
seem to yield a good value.
 
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Thread Starter

elec_eng_55

Joined May 13, 2018
214
How you define and measure this offset?



Show me the example.
What I mean is that the vout waveform starts at a voltage less than zero. Like -7 mV or -2.7 mV. It is evident in the transient graph. Perhaps the term "offset" was incorrect.
I thought that the CNF formula was yielding too low a value because a higher value seems to be needed to reduce this "offset" issue.
 
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Thread Starter

elec_eng_55

Joined May 13, 2018
214
Hi:

I still have a problem determining the required value of an emitter bypass
capacitor mathematically. See attached schematic. Using LTS, a value of
100uF works nicely but my calculated values are always much smaller,
like 8.85uF.

upload_2018-9-9_9-0-11.png

Any help would be appreciated.

David
 

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Thread Starter

elec_eng_55

Joined May 13, 2018
214
Why ?



Why 100μF wotks nicely and 8.85μF don't work for you ?
My point is this. Anyone can plug values in an LTS sim and get
lucky enough to find a good value. 8.85 uF results in a much greater
offset voltage on the output, than say 100uF. There is a way to
determine the right value mathematically. I would like to know
how to use the mathematical approach. So far with all my research,
I have not been able to find the answer.
 
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Jony130

Joined Feb 17, 2009
5,488
I cannot understand why you are so bothered about the very small "pseudo offset" in the first place? Which is not a real offset (DC voltage at the output), but a phase shift caused by a capacitor in a circuit. It's physically impossible to have an "offset voltage" (DC voltage) after the signal passes the capacitor in steady-state.

Also, when you are using this equation C = 1/(2 * pi * Fc *R) to compute the capacitor value you should keep in mind that at this frequency (Fc) the phase shift is equal to 45° degrees.

So far with all my research,
I have not been able to find the answer.
Where did you try to find this answer? You need some basic circuit theory book for sure.
 
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Thread Starter

elec_eng_55

Joined May 13, 2018
214
I cannot understand why you are so bothered about the very small "pseudo offset" in the first place? Which is not a real offset (DC voltage at the output), but a phase shift caused by a capacitor in a circuit. It's physically impossible to have an "offset voltage" (DC voltage) after the signal passes the capacitor in steady-state.

Also, when you are using this equation C = 1/(2 * pi * Fc *R) to compute the capacitor value you should keep in mind that at this frequency (Fc) the phase shift is equal to 45° degrees.


Where did you try to find this answer? You need some basic circuit theory book for sure.
Hi:

I researched Heathkit course manuals which I have thrown out since they weren't very good.
I have searched the internet but each article leaves out stuff and none of them really cover
a topic completely. At least that is the case with the stuff that I have found. I wouldn't mind
investing in a good textbook if someone can make a recommendation. The best info so far
has been on this site.

David
 

Audioguru

Joined Dec 20, 2007
11,248
I understood that the base line should always be zero volts. If the CNF formula yielded a larger capacitor value, this offset would be much smaller. Is this offset not a form of distortion?
Yes, the offset is distortion. It is normal for a single common-emitter NPN transistor to squash the positive going peak compared to the normal or extended negative-going peak. The voltage gain of the transistor is reduced when it nears cutoff. It causes even harmonics distortion.
 

Bordodynov

Joined May 20, 2015
3,181
Hi:

I still have a problem determining the required value of an emitter bypass
capacitor mathematically. See attached schematic. Using LTS, a value of
100uF works nicely but my calculated values are always much smaller,
like 8.85uF.

View attachment 159575

Any help would be appreciated.
David
In your amplifier there are three capacitors, which are high-pass filters. If you want to equalize the time constants, then
A=1/(1+1/jWC1)/(1+1/jWC2)/(1+1/jWC3) , W=2piFre
This is approximate, since the first RC and the second RC affect the dlug on the other. With a very large BETA transistor, this formula works well.
Let us take the frequency at which the attenuation is 3 dB, i.e. 1/2 ^ 0.5. ==> into one cell 1/2 ^ 1/6.
Abs(1/(1+1/jWCi))=WCi/Sqrt((WCi)^2+1)=1/2^1/6
For calc C3 Ri=RC+RL
 

Bordodynov

Joined May 20, 2015
3,181
There is another harmful effect due to the presence of a capacitor in the emitter of the transistor. This is the detection effect. This effect leads to a dynamic change in the operating point of the transistor.
 

Thread Starter

elec_eng_55

Joined May 13, 2018
214
There is another harmful effect due to the presence of a capacitor in the emitter of the transistor. This is the detection effect. This effect leads to a dynamic change in the operating point of the transistor.

Thanks for your replies folks. If anyone out there knows of a good textbook please let me know.

David
 
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