If you can't get that circuit to work, I suggest you again try the circuit in post #8.
Increase the value of C1, if necessary.
For the clock, connect the switch to V+ with a 1k resistor from the other switch connection to ground (no capacitors).

 

Hi

You can use the second FF like this.
See Attached.

 

Today I went to a brick-and-mortar store and bought a TI CD4013BE and an NXP HEF4013BP. The devices I had before are marked TI CD4013BE. The HEF4013BP works perfectly in the circuit from post #9. The new CD4013BE that I got today does not, but works in the circuit from post #8 after replacing the 100nF cap with a 1uF cap. The old CD4013BE's that I started out with only work, but now work reliably, with 100nF on the switch and 1uF on the D out put. Weird ... It seemed like such an easy circuit at first glance. But at least I'm getting somewhere now.

Anyway, thanks for the help folks!

 

Peanut gallery here - certainly not the expert on flip-flops, but it looks to me like R1 1MΩ may be too high to allow the system to reset fast enough to accept another push of the button. If your circuit works fine when you push the button every few seconds (or longer) but not when you rapidly press S1 (switch) then it might be because the 100nF cap is holding the clock signal too high too long and you're not getting a sufficient transition from low to high at the clock input.

Like I said, I'm NOT the expert on this. At best - novice. This is just my observation. May be entirely wrong. If so - someone here will quickly point out my error. For which I'm fine with that. I don't learn if not corrected.

[edit]
Assuming you're using a 12 volt power source, you don't need a 1 meg ohm resistor. Using a 100KΩ resistor for R1 will draw 120 µA (micro-amps). Using 10K will give you 1.2 mA (milli-amps). Depending on how long you want the battery to last - using a smaller resistor may give you a faster switch reset time and be ready for another switch signal input. And if you are using a 9V battery - even faster. Not sure if I missed the voltage you wish to use, but in your opening post your on line schematic shows a 12 volt source but your schematic shows a 9 volt source.

 

And yes, the clock edge speed could be the problem as seen here from the data sheet:

I think that spec is there for cases where multiple flip flops are being clocked synchronously where differences in threshold voltages would cause them to latch the wrong data.

Consider the case where you have DFF configured as a shift register. If the threshold of the clock input for the second flip flop is higher than the first, it will latch data later. If that delay is after the propagation delay of the first flip flop, it will latch the wrong data if the first flop changed state.

 

I think that spec is there for cases where multiple flip flops are being clocked synchronously where differences in threshold voltages would cause them to latch the wrong data.

Well, that's certainly a valid theory, but I think it's so the internal latches switch at the same time to avoid any possible race conditions.
That would explain why the op was having a problem when he slowed down the clock edges with the debounce circuit.

 

Not sure if I missed the voltage you wish to use, but in your opening post your on line schematic shows a 12 volt source but your schematic shows a 9 volt source.

The voltage is undecided for now. The aim is to make selectable pre-amps and I'll let the CD4013 run on whatever the pre-amps end up using. Now that I've got something to work with I'll certainly try out your suggestion.

That would explain why the op was having a problem when he slowed down the clock edges with the debounce circuit.

Maybe also why the HEF4013 worked as a drop in replacement where the CD4013 wouldn't because of the Schmitt trigger on the clock input as noted by Kjeldgaard.

 

Well, that's certainly a valid theory, but I think it's so the internal latches switch at the same time to avoid any possible race conditions.
That would explain why the op was having a problem when he slowed down the clock edges with the debounce circuit.

I once helped redesign a circuit that had a similar problem. It was a microprocessor with an external peripheral chip.

Originally, the reset circuit was just an resistor/capacitor delay going directly to the reset pins on the processor and the peripheral. The threshold voltages of parts was different. This caused the microprocessor to come out of reset before the peripheral. The result was that the software initialized the registers in the peripheral while it was still in reset.

I should have said that the software tried to initialize the peripheral. The solution was to put a gate with hysteresis between the R/C and the reset pins.

 

Your modified circuit is a real mess. Especially since the original is poor.

Focus on original schematic, try removing the capacitor and 100k resistor from the "Q-bar" output path. Connect "Q-bar" directly to "D" input.

The reason for the delay circuit from Q- to D is to meet hold time requirement. D has to be held steady not only prior to leading edge of the clock (setup time requirement) but also a bit after the clock transition (hold time requirement). The idea is to avoid second transition due to D changing prior to clock transition end. I would rather look at the de-bouncing circuit. My usual tack is to have the cap across the 1 Meg, not to GND.

 

Best of all would be to put a cap in parallel with the switch here...

View attachment 123545

Cap across the 1 Meg, 1k to GND

 

I think we can stop rehashing this.
The op stated in post #23 that the circuit works with the resistor and capacitor on the D pin.