Problem A: An isolated metal4 wire is 1.5 mm long, 0.5 um wide, and runs over a large sheet of metal2. It is driven by a CMOS driver with very fast output rise and fall times. How will the delay change for the following cases? You may give your answer in a general sense that is true for all technologies, or use 0.25 um data from book pp. 143-145 or inside cover.
So i'm confused about a small thing. The book gives an example about find the parallel plate and fringe capacitances, in that example, you have only Metal 1 and the substrate. In this problem, we are looking at metal 4 being over metal two. Do i also have to look at metal 2 when i'm calculating the fringe and parallel plate capacitance? The table gives both the top and bottom capacitor values. I took the values 6.5 and 14 for metal 4 and calculated the top plate. Do i also have to look at the metal 2 (Al2) coloumn to calculate the bottom plate. Or did i take the wrong vaues and was instead suppose to take the common capacitor value between Al4 and Al2 in order to get the proper capacitor value. Usin Al4 row values 6.5 and 14 i got: Cpp = 4.875fF and Cfringe=21fF. Am i approaching this problem right?

- [4 pts] If the wire length is doubled.
So i'm confused about a small thing. The book gives an example about find the parallel plate and fringe capacitances, in that example, you have only Metal 1 and the substrate. In this problem, we are looking at metal 4 being over metal two. Do i also have to look at metal 2 when i'm calculating the fringe and parallel plate capacitance? The table gives both the top and bottom capacitor values. I took the values 6.5 and 14 for metal 4 and calculated the top plate. Do i also have to look at the metal 2 (Al2) coloumn to calculate the bottom plate. Or did i take the wrong vaues and was instead suppose to take the common capacitor value between Al4 and Al2 in order to get the proper capacitor value. Usin Al4 row values 6.5 and 14 i got: Cpp = 4.875fF and Cfringe=21fF. Am i approaching this problem right?

